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Antonio Nino Diazf3ff9f72018-09-18 01:36:00 +01001#
Carlo Caione4a079c72019-08-23 18:28:36 +01002# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
Antonio Nino Diazf3ff9f72018-09-18 01:36:00 +01003#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7include lib/xlat_tables_v2/xlat_tables.mk
8
Carlo Caione1b250192019-08-23 19:34:44 +01009AML_PLAT := plat/amlogic
10AML_PLAT_SOC := ${AML_PLAT}/${PLAT}
Carlo Caione40fac1a2019-08-23 20:02:32 +010011AML_PLAT_COMMON := ${AML_PLAT}/common
Antonio Nino Diazf3ff9f72018-09-18 01:36:00 +010012
Carlo Caione69b315a2019-08-24 17:28:23 +010013PLAT_INCLUDES := -Iinclude/drivers/amlogic/ \
14 -I${AML_PLAT_SOC}/include \
15 -I${AML_PLAT_COMMON}/include
Carlo Caione1b250192019-08-23 19:34:44 +010016
17GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
Antonio Nino Diazf3ff9f72018-09-18 01:36:00 +010018 drivers/arm/gic/v2/gicv2_main.c \
19 drivers/arm/gic/v2/gicv2_helpers.c \
20 plat/common/plat_gicv2.c
21
Carlo Caione4a079c72019-08-23 18:28:36 +010022PLAT_BL_COMMON_SOURCES := drivers/amlogic/console/aarch64/meson_console.S \
Carlo Caione1b250192019-08-23 19:34:44 +010023 ${AML_PLAT_SOC}/gxbb_common.c \
24 ${AML_PLAT_SOC}/gxbb_topology.c \
Antonio Nino Diazf3ff9f72018-09-18 01:36:00 +010025 ${XLAT_TABLES_LIB_SRCS}
26
27BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
28 plat/common/plat_psci_common.c \
Carlo Caione40fac1a2019-08-23 20:02:32 +010029 ${AML_PLAT_COMMON}/aarch64/aml_helpers.S \
Carlo Caione1b250192019-08-23 19:34:44 +010030 ${AML_PLAT_SOC}/gxbb_bl31_setup.c \
31 ${AML_PLAT_SOC}/gxbb_efuse.c \
32 ${AML_PLAT_SOC}/gxbb_mhu.c \
33 ${AML_PLAT_SOC}/gxbb_pm.c \
Carlo Caione69b315a2019-08-24 17:28:23 +010034 ${AML_PLAT_COMMON}/aml_scpi.c \
Carlo Caione1b250192019-08-23 19:34:44 +010035 ${AML_PLAT_SOC}/gxbb_sip_svc.c \
36 ${AML_PLAT_SOC}/gxbb_thermal.c \
37 ${GIC_SOURCES}
Antonio Nino Diazf3ff9f72018-09-18 01:36:00 +010038
39# Tune compiler for Cortex-A53
40ifeq ($(notdir $(CC)),armclang)
41 TF_CFLAGS_aarch64 += -mcpu=cortex-a53
42else ifneq ($(findstring clang,$(notdir $(CC))),)
43 TF_CFLAGS_aarch64 += -mcpu=cortex-a53
44else
45 TF_CFLAGS_aarch64 += -mtune=cortex-a53
46endif
47
48# Build config flags
49# ------------------
50
51# Enable all errata workarounds for Cortex-A53
52ERRATA_A53_826319 := 1
53ERRATA_A53_835769 := 1
54ERRATA_A53_836870 := 1
55ERRATA_A53_843419 := 1
56ERRATA_A53_855873 := 1
57
58WORKAROUND_CVE_2017_5715 := 0
59
60# Have different sections for code and rodata
61SEPARATE_CODE_AND_RODATA := 1
62
63# Use Coherent memory
64USE_COHERENT_MEM := 1
65
Antonio Nino Diazf3ff9f72018-09-18 01:36:00 +010066# Verify build config
67# -------------------
68
Antonio Nino Diazf3ff9f72018-09-18 01:36:00 +010069ifneq (${RESET_TO_BL31}, 0)
Carlo Caione1b250192019-08-23 19:34:44 +010070 $(error Error: ${PLAT} needs RESET_TO_BL31=0)
Antonio Nino Diazf3ff9f72018-09-18 01:36:00 +010071endif
72
73ifeq (${ARCH},aarch32)
Carlo Caione1b250192019-08-23 19:34:44 +010074 $(error Error: AArch32 not supported on ${PLAT})
Antonio Nino Diazf3ff9f72018-09-18 01:36:00 +010075endif