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review.trustedfirmware.org / TF-A / trusted-firmware-a / 70b0f2789e93f253bec5cbd2986d0de023c1bdf4 / . / plat / nvidia / tegra / include / platform_def.h
blob: 334ad129a196385d2edfcdd1f5cb449c8d1720e2 [file] [log] [blame]
Varun Wadekar08438e22015-05-19 16:48:04 +0530[diff] [blame]1/*
Steven Kao1d11f732018-02-09 20:50:02 +0800[diff] [blame]2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Varun Wadekar08438e22015-05-19 16:48:04 +0530[diff] [blame]3 *
dp-arm82cb2c12017-05-03 09:38:09 +0100[diff] [blame]4 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekar08438e22015-05-19 16:48:04 +0530[diff] [blame]5 */
6
Antonio Nino Diazc3cf06f2018-11-08 10:20:19 +0000[diff] [blame]7#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
Varun Wadekar08438e22015-05-19 16:48:04 +0530[diff] [blame]9
10#include <arch.h>
Antonio Nino Diaz09d40e02018-12-14 00:18:21 +0000[diff] [blame]11#include <lib/utils_def.h>
12#include <plat/common/common_def.h>
13
Varun Wadekar71cb26e2015-08-07 10:03:00 +0530[diff] [blame]14#include <tegra_def.h>
Varun Wadekar08438e22015-05-19 16:48:04 +0530[diff] [blame]15
16/*******************************************************************************
17 * Generic platform constants
18 ******************************************************************************/
19
20/* Size of cacheable stacks */
Masahiro Yamada3d8256b2016-12-25 23:36:24 +0900[diff] [blame]21#ifdef IMAGE_BL31
Varun Wadekar70cb6922017-04-24 14:17:12 -0700[diff] [blame]22#define PLATFORM_STACK_SIZE U(0x400)
Varun Wadekar08438e22015-05-19 16:48:04 +0530[diff] [blame]23#endif
24
Varun Wadekar70cb6922017-04-24 14:17:12 -0700[diff] [blame]25#define TEGRA_PRIMARY_CPU U(0x0)
Varun Wadekar08438e22015-05-19 16:48:04 +0530[diff] [blame]26
Varun Wadekar71cb26e2015-08-07 10:03:00 +0530[diff] [blame]27#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
Varun Wadekar43ec35e2015-08-12 09:24:50 +0530[diff] [blame]28#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
29 PLATFORM_MAX_CPUS_PER_CLUSTER)
Varun Wadekar71cb26e2015-08-07 10:03:00 +0530[diff] [blame]30#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
Varun Wadekar43ec35e2015-08-12 09:24:50 +0530[diff] [blame]31 PLATFORM_CLUSTER_COUNT + 1)
Varun Wadekar08438e22015-05-19 16:48:04 +0530[diff] [blame]32
33/*******************************************************************************
34 * Platform console related constants
35 ******************************************************************************/
Varun Wadekar70cb6922017-04-24 14:17:12 -0700[diff] [blame]36#define TEGRA_CONSOLE_BAUDRATE U(115200)
Harvey Hsieh322e7c32017-04-10 16:20:32 +0800[diff] [blame]37#define TEGRA_BOOT_UART_CLK_13_MHZ U(13000000)
38#define TEGRA_BOOT_UART_CLK_408_MHZ U(408000000)
Varun Wadekar08438e22015-05-19 16:48:04 +0530[diff] [blame]39
40/*******************************************************************************
41 * Platform memory map related constants
42 ******************************************************************************/
43/* Size of trusted dram */
Varun Wadekar70cb6922017-04-24 14:17:12 -0700[diff] [blame]44#define TZDRAM_SIZE U(0x00400000)
Varun Wadekar08438e22015-05-19 16:48:04 +0530[diff] [blame]45#define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE)
46
47/*******************************************************************************
48 * BL31 specific defines.
49 ******************************************************************************/
Varun Wadekar70cb6922017-04-24 14:17:12 -0700[diff] [blame]50#define BL31_SIZE U(0x40000)
Varun Wadekar08438e22015-05-19 16:48:04 +0530[diff] [blame]51#define BL31_BASE TZDRAM_BASE
Varun Wadekardc7fdad2015-06-05 12:57:27 +0530[diff] [blame]52#define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1)
53#define BL32_BASE (TZDRAM_BASE + BL31_SIZE)
54#define BL32_LIMIT TZDRAM_END
Varun Wadekar08438e22015-05-19 16:48:04 +0530[diff] [blame]55
56/*******************************************************************************
Varun Wadekar08438e22015-05-19 16:48:04 +0530[diff] [blame]57 * Some data must be aligned on the biggest cache line size in the platform.
58 * This is known only to the platform as it might have a combination of
59 * integrated and external caches.
60 ******************************************************************************/
61#define CACHE_WRITEBACK_SHIFT 6
Varun Wadekar70cb6922017-04-24 14:17:12 -0700[diff] [blame]62#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
Varun Wadekar08438e22015-05-19 16:48:04 +0530[diff] [blame]63
Antonio Nino Diazc3cf06f2018-11-08 10:20:19 +0000[diff] [blame]64#endif /* PLATFORM_DEF_H */