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Ghennadi Procopciuc66af5422024-06-12 09:07:16 +03001/*
2 * Copyright 2024 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6#include <drivers/clk.h>
7#include <s32cc-clk-drv.h>
8#include <s32cc-clk-ids.h>
9#include <s32cc-clk-utils.h>
10
11#define S32CC_FXOSC_FREQ (40U * MHZ)
Ghennadi Procopciuc7ad4e232024-06-12 11:55:32 +030012#define S32CC_ARM_PLL_VCO_FREQ (2U * GHZ)
Ghennadi Procopciuc66af5422024-06-12 09:07:16 +030013
14int s32cc_init_early_clks(void)
15{
16 int ret;
17
18 s32cc_clk_register_drv();
19
Ghennadi Procopciuc83af4502024-06-12 11:17:37 +030020 ret = clk_set_parent(S32CC_CLK_ARM_PLL_MUX, S32CC_CLK_FXOSC);
21 if (ret != 0) {
22 return ret;
23 }
24
25 ret = clk_set_parent(S32CC_CLK_MC_CGM1_MUX0, S32CC_CLK_ARM_PLL_PHI0);
26 if (ret != 0) {
27 return ret;
28 }
29
Ghennadi Procopciuc66af5422024-06-12 09:07:16 +030030 ret = clk_set_rate(S32CC_CLK_FXOSC, S32CC_FXOSC_FREQ, NULL);
31 if (ret != 0) {
32 return ret;
33 }
34
Ghennadi Procopciuc7ad4e232024-06-12 11:55:32 +030035 ret = clk_set_rate(S32CC_CLK_ARM_PLL_VCO, S32CC_ARM_PLL_VCO_FREQ, NULL);
36 if (ret != 0) {
37 return ret;
38 }
39
Ghennadi Procopciuc8ab34352024-06-12 09:25:17 +030040 ret = clk_enable(S32CC_CLK_FXOSC);
41 if (ret != 0) {
42 return ret;
43 }
44
Ghennadi Procopciuc66af5422024-06-12 09:07:16 +030045 return ret;
46}