Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | e83b0ca | 2014-01-14 18:17:09 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Dan Handley | 97043ac | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 31 | #include <arch.h> |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 32 | #include <asm_macros.S> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 33 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 34 | .globl read_vbar_el1 |
| 35 | .globl read_vbar_el2 |
| 36 | .globl read_vbar_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 37 | .globl write_vbar_el1 |
| 38 | .globl write_vbar_el2 |
| 39 | .globl write_vbar_el3 |
| 40 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 41 | .globl read_sctlr_el1 |
| 42 | .globl read_sctlr_el2 |
| 43 | .globl read_sctlr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 44 | .globl write_sctlr_el1 |
| 45 | .globl write_sctlr_el2 |
| 46 | .globl write_sctlr_el3 |
| 47 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 48 | .globl read_actlr_el1 |
| 49 | .globl read_actlr_el2 |
| 50 | .globl read_actlr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 51 | .globl write_actlr_el1 |
| 52 | .globl write_actlr_el2 |
| 53 | .globl write_actlr_el3 |
| 54 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 55 | .globl read_esr_el1 |
| 56 | .globl read_esr_el2 |
| 57 | .globl read_esr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 58 | .globl write_esr_el1 |
| 59 | .globl write_esr_el2 |
| 60 | .globl write_esr_el3 |
| 61 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 62 | .globl read_afsr0_el1 |
| 63 | .globl read_afsr0_el2 |
| 64 | .globl read_afsr0_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 65 | .globl write_afsr0_el1 |
| 66 | .globl write_afsr0_el2 |
| 67 | .globl write_afsr0_el3 |
| 68 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 69 | .globl read_afsr1_el1 |
| 70 | .globl read_afsr1_el2 |
| 71 | .globl read_afsr1_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 72 | .globl write_afsr1_el1 |
| 73 | .globl write_afsr1_el2 |
| 74 | .globl write_afsr1_el3 |
| 75 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 76 | .globl read_far_el1 |
| 77 | .globl read_far_el2 |
| 78 | .globl read_far_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 79 | .globl write_far_el1 |
| 80 | .globl write_far_el2 |
| 81 | .globl write_far_el3 |
| 82 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 83 | .globl read_mair_el1 |
| 84 | .globl read_mair_el2 |
| 85 | .globl read_mair_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 86 | .globl write_mair_el1 |
| 87 | .globl write_mair_el2 |
| 88 | .globl write_mair_el3 |
| 89 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 90 | .globl read_amair_el1 |
| 91 | .globl read_amair_el2 |
| 92 | .globl read_amair_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 93 | .globl write_amair_el1 |
| 94 | .globl write_amair_el2 |
| 95 | .globl write_amair_el3 |
| 96 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 97 | .globl read_rvbar_el1 |
| 98 | .globl read_rvbar_el2 |
| 99 | .globl read_rvbar_el3 |
| 100 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 101 | .globl read_rmr_el1 |
| 102 | .globl read_rmr_el2 |
| 103 | .globl read_rmr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 104 | .globl write_rmr_el1 |
| 105 | .globl write_rmr_el2 |
| 106 | .globl write_rmr_el3 |
| 107 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 108 | .globl read_tcr_el1 |
| 109 | .globl read_tcr_el2 |
| 110 | .globl read_tcr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 111 | .globl write_tcr_el1 |
| 112 | .globl write_tcr_el2 |
| 113 | .globl write_tcr_el3 |
| 114 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 115 | .globl read_cptr_el2 |
| 116 | .globl read_cptr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 117 | .globl write_cptr_el2 |
| 118 | .globl write_cptr_el3 |
| 119 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 120 | .globl read_ttbr0_el1 |
| 121 | .globl read_ttbr0_el2 |
| 122 | .globl read_ttbr0_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 123 | .globl write_ttbr0_el1 |
| 124 | .globl write_ttbr0_el2 |
| 125 | .globl write_ttbr0_el3 |
| 126 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 127 | .globl read_ttbr1_el1 |
| 128 | .globl read_ttbr1_el2 |
| 129 | .globl write_ttbr1 |
| 130 | .globl write_ttbr1_el1 |
| 131 | .globl write_ttbr1_el2 |
| 132 | |
| 133 | .globl read_cpacr |
| 134 | .globl write_cpacr |
| 135 | |
| 136 | .globl read_cntfrq |
| 137 | .globl write_cntfrq |
| 138 | |
| 139 | .globl read_cpuectlr |
| 140 | .globl write_cpuectlr |
| 141 | |
| 142 | .globl read_cnthctl_el2 |
| 143 | .globl write_cnthctl_el2 |
| 144 | |
| 145 | .globl read_cntfrq_el0 |
| 146 | .globl write_cntfrq_el0 |
| 147 | |
| 148 | .globl read_scr |
| 149 | .globl write_scr |
| 150 | |
| 151 | .globl read_hcr |
| 152 | .globl write_hcr |
| 153 | |
| 154 | .globl read_midr |
| 155 | .globl read_mpidr |
| 156 | |
| 157 | .globl read_current_el |
| 158 | .globl read_id_pfr1_el1 |
| 159 | .globl read_id_aa64pfr0_el1 |
| 160 | |
| 161 | #if SUPPORT_VFP |
| 162 | .globl enable_vfp |
| 163 | .globl read_fpexc |
| 164 | .globl write_fpexc |
| 165 | #endif |
| 166 | |
| 167 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 168 | func read_current_el |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 169 | mrs x0, CurrentEl |
| 170 | ret |
| 171 | |
| 172 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 173 | func read_id_pfr1_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 174 | mrs x0, id_pfr1_el1 |
| 175 | ret |
| 176 | |
| 177 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 178 | func read_id_aa64pfr0_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 179 | mrs x0, id_aa64pfr0_el1 |
| 180 | ret |
| 181 | |
| 182 | |
| 183 | /* ----------------------------------------------------- |
| 184 | * VBAR accessors |
| 185 | * ----------------------------------------------------- |
| 186 | */ |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 187 | func read_vbar_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 188 | mrs x0, vbar_el1 |
| 189 | ret |
| 190 | |
| 191 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 192 | func read_vbar_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 193 | mrs x0, vbar_el2 |
| 194 | ret |
| 195 | |
| 196 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 197 | func read_vbar_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 198 | mrs x0, vbar_el3 |
| 199 | ret |
| 200 | |
| 201 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 202 | func write_vbar_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 203 | msr vbar_el1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 204 | ret |
| 205 | |
| 206 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 207 | func write_vbar_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 208 | msr vbar_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 209 | ret |
| 210 | |
| 211 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 212 | func write_vbar_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 213 | msr vbar_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 214 | ret |
| 215 | |
| 216 | |
| 217 | /* ----------------------------------------------------- |
| 218 | * AFSR0 accessors |
| 219 | * ----------------------------------------------------- |
| 220 | */ |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 221 | func read_afsr0_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 222 | mrs x0, afsr0_el1 |
| 223 | ret |
| 224 | |
| 225 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 226 | func read_afsr0_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 227 | mrs x0, afsr0_el2 |
| 228 | ret |
| 229 | |
| 230 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 231 | func read_afsr0_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 232 | mrs x0, afsr0_el3 |
| 233 | ret |
| 234 | |
| 235 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 236 | func write_afsr0_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 237 | msr afsr0_el1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 238 | ret |
| 239 | |
| 240 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 241 | func write_afsr0_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 242 | msr afsr0_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 243 | ret |
| 244 | |
| 245 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 246 | func write_afsr0_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 247 | msr afsr0_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 248 | ret |
| 249 | |
| 250 | |
| 251 | /* ----------------------------------------------------- |
| 252 | * FAR accessors |
| 253 | * ----------------------------------------------------- |
| 254 | */ |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 255 | func read_far_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 256 | mrs x0, far_el1 |
| 257 | ret |
| 258 | |
| 259 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 260 | func read_far_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 261 | mrs x0, far_el2 |
| 262 | ret |
| 263 | |
| 264 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 265 | func read_far_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 266 | mrs x0, far_el3 |
| 267 | ret |
| 268 | |
| 269 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 270 | func write_far_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 271 | msr far_el1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 272 | ret |
| 273 | |
| 274 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 275 | func write_far_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 276 | msr far_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 277 | ret |
| 278 | |
| 279 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 280 | func write_far_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 281 | msr far_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 282 | ret |
| 283 | |
| 284 | |
| 285 | /* ----------------------------------------------------- |
| 286 | * MAIR accessors |
| 287 | * ----------------------------------------------------- |
| 288 | */ |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 289 | func read_mair_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 290 | mrs x0, mair_el1 |
| 291 | ret |
| 292 | |
| 293 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 294 | func read_mair_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 295 | mrs x0, mair_el2 |
| 296 | ret |
| 297 | |
| 298 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 299 | func read_mair_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 300 | mrs x0, mair_el3 |
| 301 | ret |
| 302 | |
| 303 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 304 | func write_mair_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 305 | msr mair_el1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 306 | ret |
| 307 | |
| 308 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 309 | func write_mair_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 310 | msr mair_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 311 | ret |
| 312 | |
| 313 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 314 | func write_mair_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 315 | msr mair_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 316 | ret |
| 317 | |
| 318 | |
| 319 | /* ----------------------------------------------------- |
| 320 | * AMAIR accessors |
| 321 | * ----------------------------------------------------- |
| 322 | */ |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 323 | func read_amair_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 324 | mrs x0, amair_el1 |
| 325 | ret |
| 326 | |
| 327 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 328 | func read_amair_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 329 | mrs x0, amair_el2 |
| 330 | ret |
| 331 | |
| 332 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 333 | func read_amair_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 334 | mrs x0, amair_el3 |
| 335 | ret |
| 336 | |
| 337 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 338 | func write_amair_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 339 | msr amair_el1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 340 | ret |
| 341 | |
| 342 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 343 | func write_amair_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 344 | msr amair_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 345 | ret |
| 346 | |
| 347 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 348 | func write_amair_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 349 | msr amair_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 350 | ret |
| 351 | |
| 352 | |
| 353 | /* ----------------------------------------------------- |
| 354 | * RVBAR accessors |
| 355 | * ----------------------------------------------------- |
| 356 | */ |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 357 | func read_rvbar_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 358 | mrs x0, rvbar_el1 |
| 359 | ret |
| 360 | |
| 361 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 362 | func read_rvbar_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 363 | mrs x0, rvbar_el2 |
| 364 | ret |
| 365 | |
| 366 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 367 | func read_rvbar_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 368 | mrs x0, rvbar_el3 |
| 369 | ret |
| 370 | |
| 371 | |
| 372 | /* ----------------------------------------------------- |
| 373 | * RMR accessors |
| 374 | * ----------------------------------------------------- |
| 375 | */ |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 376 | func read_rmr_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 377 | mrs x0, rmr_el1 |
| 378 | ret |
| 379 | |
| 380 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 381 | func read_rmr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 382 | mrs x0, rmr_el2 |
| 383 | ret |
| 384 | |
| 385 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 386 | func read_rmr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 387 | mrs x0, rmr_el3 |
| 388 | ret |
| 389 | |
| 390 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 391 | func write_rmr_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 392 | msr rmr_el1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 393 | ret |
| 394 | |
| 395 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 396 | func write_rmr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 397 | msr rmr_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 398 | ret |
| 399 | |
| 400 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 401 | func write_rmr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 402 | msr rmr_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 403 | ret |
| 404 | |
| 405 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 406 | /* ----------------------------------------------------- |
| 407 | * AFSR1 accessors |
| 408 | * ----------------------------------------------------- |
| 409 | */ |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 410 | func read_afsr1_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 411 | mrs x0, afsr1_el1 |
| 412 | ret |
| 413 | |
| 414 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 415 | func read_afsr1_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 416 | mrs x0, afsr1_el2 |
| 417 | ret |
| 418 | |
| 419 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 420 | func read_afsr1_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 421 | mrs x0, afsr1_el3 |
| 422 | ret |
| 423 | |
| 424 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 425 | func write_afsr1_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 426 | msr afsr1_el1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 427 | ret |
| 428 | |
| 429 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 430 | func write_afsr1_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 431 | msr afsr1_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 432 | ret |
| 433 | |
| 434 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 435 | func write_afsr1_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 436 | msr afsr1_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 437 | ret |
| 438 | |
| 439 | |
| 440 | /* ----------------------------------------------------- |
| 441 | * SCTLR accessors |
| 442 | * ----------------------------------------------------- |
| 443 | */ |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 444 | func read_sctlr_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 445 | mrs x0, sctlr_el1 |
| 446 | ret |
| 447 | |
| 448 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 449 | func read_sctlr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 450 | mrs x0, sctlr_el2 |
| 451 | ret |
| 452 | |
| 453 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 454 | func read_sctlr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 455 | mrs x0, sctlr_el3 |
| 456 | ret |
| 457 | |
| 458 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 459 | func write_sctlr_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 460 | msr sctlr_el1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 461 | ret |
| 462 | |
| 463 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 464 | func write_sctlr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 465 | msr sctlr_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 466 | ret |
| 467 | |
| 468 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 469 | func write_sctlr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 470 | msr sctlr_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 471 | ret |
| 472 | |
| 473 | |
| 474 | /* ----------------------------------------------------- |
| 475 | * ACTLR accessors |
| 476 | * ----------------------------------------------------- |
| 477 | */ |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 478 | func read_actlr_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 479 | mrs x0, actlr_el1 |
| 480 | ret |
| 481 | |
| 482 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 483 | func read_actlr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 484 | mrs x0, actlr_el2 |
| 485 | ret |
| 486 | |
| 487 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 488 | func read_actlr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 489 | mrs x0, actlr_el3 |
| 490 | ret |
| 491 | |
| 492 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 493 | func write_actlr_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 494 | msr actlr_el1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 495 | ret |
| 496 | |
| 497 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 498 | func write_actlr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 499 | msr actlr_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 500 | ret |
| 501 | |
| 502 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 503 | func write_actlr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 504 | msr actlr_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 505 | ret |
| 506 | |
| 507 | |
| 508 | /* ----------------------------------------------------- |
| 509 | * ESR accessors |
| 510 | * ----------------------------------------------------- |
| 511 | */ |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 512 | func read_esr_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 513 | mrs x0, esr_el1 |
| 514 | ret |
| 515 | |
| 516 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 517 | func read_esr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 518 | mrs x0, esr_el2 |
| 519 | ret |
| 520 | |
| 521 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 522 | func read_esr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 523 | mrs x0, esr_el3 |
| 524 | ret |
| 525 | |
| 526 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 527 | func write_esr_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 528 | msr esr_el1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 529 | ret |
| 530 | |
| 531 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 532 | func write_esr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 533 | msr esr_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 534 | ret |
| 535 | |
| 536 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 537 | func write_esr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 538 | msr esr_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 539 | ret |
| 540 | |
| 541 | |
| 542 | /* ----------------------------------------------------- |
| 543 | * TCR accessors |
| 544 | * ----------------------------------------------------- |
| 545 | */ |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 546 | func read_tcr_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 547 | mrs x0, tcr_el1 |
| 548 | ret |
| 549 | |
| 550 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 551 | func read_tcr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 552 | mrs x0, tcr_el2 |
| 553 | ret |
| 554 | |
| 555 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 556 | func read_tcr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 557 | mrs x0, tcr_el3 |
| 558 | ret |
| 559 | |
| 560 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 561 | func write_tcr_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 562 | msr tcr_el1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 563 | ret |
| 564 | |
| 565 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 566 | func write_tcr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 567 | msr tcr_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 568 | ret |
| 569 | |
| 570 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 571 | func write_tcr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 572 | msr tcr_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 573 | ret |
| 574 | |
| 575 | |
| 576 | /* ----------------------------------------------------- |
| 577 | * CPTR accessors |
| 578 | * ----------------------------------------------------- |
| 579 | */ |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 580 | func read_cptr_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 581 | b read_cptr_el1 |
| 582 | ret |
| 583 | |
| 584 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 585 | func read_cptr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 586 | mrs x0, cptr_el2 |
| 587 | ret |
| 588 | |
| 589 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 590 | func read_cptr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 591 | mrs x0, cptr_el3 |
| 592 | ret |
| 593 | |
| 594 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 595 | func write_cptr_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 596 | b write_cptr_el1 |
| 597 | |
| 598 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 599 | func write_cptr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 600 | msr cptr_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 601 | ret |
| 602 | |
| 603 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 604 | func write_cptr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 605 | msr cptr_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 606 | ret |
| 607 | |
| 608 | |
| 609 | /* ----------------------------------------------------- |
| 610 | * TTBR0 accessors |
| 611 | * ----------------------------------------------------- |
| 612 | */ |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 613 | func read_ttbr0_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 614 | mrs x0, ttbr0_el1 |
| 615 | ret |
| 616 | |
| 617 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 618 | func read_ttbr0_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 619 | mrs x0, ttbr0_el2 |
| 620 | ret |
| 621 | |
| 622 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 623 | func read_ttbr0_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 624 | mrs x0, ttbr0_el3 |
| 625 | ret |
| 626 | |
| 627 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 628 | func write_ttbr0_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 629 | msr ttbr0_el1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 630 | ret |
| 631 | |
| 632 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 633 | func write_ttbr0_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 634 | msr ttbr0_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 635 | ret |
| 636 | |
| 637 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 638 | func write_ttbr0_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 639 | msr ttbr0_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 640 | ret |
| 641 | |
| 642 | |
| 643 | /* ----------------------------------------------------- |
| 644 | * TTBR1 accessors |
| 645 | * ----------------------------------------------------- |
| 646 | */ |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 647 | func read_ttbr1_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 648 | mrs x0, ttbr1_el1 |
| 649 | ret |
| 650 | |
| 651 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 652 | func read_ttbr1_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 653 | b read_ttbr1_el2 |
| 654 | |
| 655 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 656 | func read_ttbr1_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 657 | b read_ttbr1_el3 |
| 658 | |
| 659 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 660 | func write_ttbr1_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 661 | msr ttbr1_el1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 662 | ret |
| 663 | |
| 664 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 665 | func write_ttbr1_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 666 | b write_ttbr1_el2 |
| 667 | |
| 668 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 669 | func write_ttbr1_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 670 | b write_ttbr1_el3 |
| 671 | |
| 672 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 673 | func read_hcr |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 674 | mrs x0, hcr_el2 |
| 675 | ret |
| 676 | |
| 677 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 678 | func write_hcr |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 679 | msr hcr_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 680 | ret |
| 681 | |
| 682 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 683 | func read_cpacr |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 684 | mrs x0, cpacr_el1 |
| 685 | ret |
| 686 | |
| 687 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 688 | func write_cpacr |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 689 | msr cpacr_el1, x0 |
| 690 | ret |
| 691 | |
| 692 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 693 | func read_cntfrq_el0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 694 | mrs x0, cntfrq_el0 |
| 695 | ret |
| 696 | |
| 697 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 698 | func write_cntfrq_el0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 699 | msr cntfrq_el0, x0 |
| 700 | ret |
| 701 | |
| 702 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 703 | func read_cpuectlr |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 704 | mrs x0, CPUECTLR_EL1 |
| 705 | ret |
| 706 | |
| 707 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 708 | func write_cpuectlr |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 709 | msr CPUECTLR_EL1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 710 | ret |
| 711 | |
| 712 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 713 | func read_cnthctl_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 714 | mrs x0, cnthctl_el2 |
| 715 | ret |
| 716 | |
| 717 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 718 | func write_cnthctl_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 719 | msr cnthctl_el2, x0 |
| 720 | ret |
| 721 | |
| 722 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 723 | func read_cntfrq |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 724 | mrs x0, cntfrq_el0 |
| 725 | ret |
| 726 | |
| 727 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 728 | func write_cntfrq |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 729 | msr cntfrq_el0, x0 |
| 730 | ret |
| 731 | |
| 732 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 733 | func write_scr |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 734 | msr scr_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 735 | ret |
| 736 | |
| 737 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 738 | func read_scr |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 739 | mrs x0, scr_el3 |
| 740 | ret |
| 741 | |
| 742 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 743 | func read_midr |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 744 | mrs x0, midr_el1 |
| 745 | ret |
| 746 | |
| 747 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 748 | func read_mpidr |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 749 | mrs x0, mpidr_el1 |
| 750 | ret |
| 751 | |
| 752 | |
| 753 | #if SUPPORT_VFP |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 754 | func enable_vfp |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 755 | mrs x0, cpacr_el1 |
| 756 | orr x0, x0, #CPACR_VFP_BITS |
| 757 | msr cpacr_el1, x0 |
| 758 | mrs x0, cptr_el3 |
| 759 | mov x1, #AARCH64_CPTR_TFP |
| 760 | bic x0, x0, x1 |
| 761 | msr cptr_el3, x0 |
Andrew Thoelke | 8cec598 | 2014-04-28 12:28:39 +0100 | [diff] [blame^] | 762 | isb |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 763 | ret |
| 764 | |
| 765 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 766 | func read_fpexc |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 767 | b read_fpexc |
| 768 | ret |
| 769 | |
| 770 | |
Andrew Thoelke | 0a30cf5 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 771 | func write_fpexc |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 772 | b write_fpexc |
| 773 | ret |
| 774 | |
| 775 | #endif |