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review.trustedfirmware.org / TF-A / trusted-firmware-a / 8d56e24bb397cacbc8dc47b43ce64f35c06afb04 / . / plat / nvidia / tegra / include / platform_def.h
blob: eb55def4a509110ba57c69e42150ab97d790a942 [file] [log] [blame]
Varun Wadekar08438e22015-05-19 16:48:04 +0530[diff] [blame]1/*
Steven Kao1d11f732018-02-09 20:50:02 +0800[diff] [blame]2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Varun Wadekar08438e22015-05-19 16:48:04 +0530[diff] [blame]3 *
dp-arm82cb2c12017-05-03 09:38:09 +0100[diff] [blame]4 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekar08438e22015-05-19 16:48:04 +0530[diff] [blame]5 */
6
Antonio Nino Diazc3cf06f2018-11-08 10:20:19 +0000[diff] [blame]7#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
Varun Wadekar08438e22015-05-19 16:48:04 +0530[diff] [blame]9
10#include <arch.h>
Antonio Nino Diaz09d40e02018-12-14 00:18:21 +0000[diff] [blame]11#include <lib/utils_def.h>
Antonio Nino Diaz09d40e02018-12-14 00:18:21 +0000[diff] [blame]12
Varun Wadekar71cb26e2015-08-07 10:03:00 +0530[diff] [blame]13#include <tegra_def.h>
Varun Wadekar08438e22015-05-19 16:48:04 +0530[diff] [blame]14
Varun Wadekar9c2eda02018-12-21 10:55:42 -0800[diff] [blame]15/*
16 * Platform binary types for linking
17 */
18#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
19#define PLATFORM_LINKER_ARCH aarch64
20
Varun Wadekar08438e22015-05-19 16:48:04 +0530[diff] [blame]21/*******************************************************************************
22 * Generic platform constants
23 ******************************************************************************/
24
25/* Size of cacheable stacks */
Masahiro Yamada3d8256b2016-12-25 23:36:24 +0900[diff] [blame]26#ifdef IMAGE_BL31
Varun Wadekar70cb6922017-04-24 14:17:12 -0700[diff] [blame]27#define PLATFORM_STACK_SIZE U(0x400)
Varun Wadekar08438e22015-05-19 16:48:04 +0530[diff] [blame]28#endif
29
Varun Wadekar70cb6922017-04-24 14:17:12 -0700[diff] [blame]30#define TEGRA_PRIMARY_CPU U(0x0)
Varun Wadekar08438e22015-05-19 16:48:04 +0530[diff] [blame]31
Varun Wadekar71cb26e2015-08-07 10:03:00 +0530[diff] [blame]32#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
Varun Wadekar43ec35e2015-08-12 09:24:50 +0530[diff] [blame]33#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
34 PLATFORM_MAX_CPUS_PER_CLUSTER)
Varun Wadekar71cb26e2015-08-07 10:03:00 +0530[diff] [blame]35#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
Varun Wadekar43ec35e2015-08-12 09:24:50 +0530[diff] [blame]36 PLATFORM_CLUSTER_COUNT + 1)
Varun Wadekar08438e22015-05-19 16:48:04 +0530[diff] [blame]37
38/*******************************************************************************
39 * Platform console related constants
40 ******************************************************************************/
Varun Wadekar70cb6922017-04-24 14:17:12 -0700[diff] [blame]41#define TEGRA_CONSOLE_BAUDRATE U(115200)
Harvey Hsieh322e7c32017-04-10 16:20:32 +0800[diff] [blame]42#define TEGRA_BOOT_UART_CLK_13_MHZ U(13000000)
43#define TEGRA_BOOT_UART_CLK_408_MHZ U(408000000)
Varun Wadekar08438e22015-05-19 16:48:04 +0530[diff] [blame]44
45/*******************************************************************************
46 * Platform memory map related constants
47 ******************************************************************************/
48/* Size of trusted dram */
Varun Wadekar70cb6922017-04-24 14:17:12 -0700[diff] [blame]49#define TZDRAM_SIZE U(0x00400000)
Varun Wadekar08438e22015-05-19 16:48:04 +0530[diff] [blame]50#define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE)
51
52/*******************************************************************************
53 * BL31 specific defines.
54 ******************************************************************************/
Varun Wadekar70cb6922017-04-24 14:17:12 -0700[diff] [blame]55#define BL31_SIZE U(0x40000)
Varun Wadekar08438e22015-05-19 16:48:04 +0530[diff] [blame]56#define BL31_BASE TZDRAM_BASE
Varun Wadekardc7fdad2015-06-05 12:57:27 +0530[diff] [blame]57#define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1)
58#define BL32_BASE (TZDRAM_BASE + BL31_SIZE)
59#define BL32_LIMIT TZDRAM_END
Varun Wadekar08438e22015-05-19 16:48:04 +0530[diff] [blame]60
61/*******************************************************************************
Varun Wadekar08438e22015-05-19 16:48:04 +0530[diff] [blame]62 * Some data must be aligned on the biggest cache line size in the platform.
63 * This is known only to the platform as it might have a combination of
64 * integrated and external caches.
65 ******************************************************************************/
66#define CACHE_WRITEBACK_SHIFT 6
Kalyani Chidambaram636fcb02018-12-14 11:36:43 -0800[diff] [blame]67#define CACHE_WRITEBACK_GRANULE (0x40) /* (U(1) << CACHE_WRITEBACK_SHIFT) */
Varun Wadekar08438e22015-05-19 16:48:04 +0530[diff] [blame]68
Varun Wadekar8d56e242019-03-01 10:18:35 -0800[diff] [blame^]69/*******************************************************************************
70 * Dummy macros to compile io_storage support
71 ******************************************************************************/
72#define MAX_IO_DEVICES U(0)
73#define MAX_IO_HANDLES U(0)
74
Antonio Nino Diazc3cf06f2018-11-08 10:20:19 +0000[diff] [blame]75#endif /* PLATFORM_DEF_H */