| Yann Gautier | 10a511c | 2018-07-24 17:18:19 +0200 | [diff] [blame] | 1 | /* |
| Yann Gautier | 88f4fb8 | 2020-09-17 12:42:46 +0200 | [diff] [blame] | 2 | * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved |
| Yann Gautier | 10a511c | 2018-07-24 17:18:19 +0200 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause | ||||
| 5 | */ | ||||
| 6 | |||||
| Antonio Nino Diaz | 09d40e0 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 7 | #include <drivers/st/stm32mp1_ddr_helpers.h> |
| Antonio Nino Diaz | 09d40e0 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | #include <lib/mmio.h> |
| Yann Gautier | 10a511c | 2018-07-24 17:18:19 +0200 | [diff] [blame] | 9 | |
| Yann Gautier | 88f4fb8 | 2020-09-17 12:42:46 +0200 | [diff] [blame] | 10 | #include <platform_def.h> |
| 11 | |||||
| Yann Gautier | 10a511c | 2018-07-24 17:18:19 +0200 | [diff] [blame] | 12 | void ddr_enable_clock(void) |
| 13 | { | ||||
| Yann Gautier | 0d21680 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 14 | stm32mp1_clk_rcc_regs_lock(); |
| 15 | |||||
| Yann Gautier | 7ae58c6 | 2019-02-14 11:01:20 +0100 | [diff] [blame] | 16 | mmio_setbits_32(stm32mp_rcc_base() + RCC_DDRITFCR, |
| Yann Gautier | 10a511c | 2018-07-24 17:18:19 +0200 | [diff] [blame] | 17 | RCC_DDRITFCR_DDRC1EN | |
| Yann Gautier | 88f4fb8 | 2020-09-17 12:42:46 +0200 | [diff] [blame] | 18 | #if STM32MP_DDR_DUAL_AXI_PORT |
| Yann Gautier | 10a511c | 2018-07-24 17:18:19 +0200 | [diff] [blame] | 19 | RCC_DDRITFCR_DDRC2EN | |
| Yann Gautier | 88f4fb8 | 2020-09-17 12:42:46 +0200 | [diff] [blame] | 20 | #endif |
| Yann Gautier | 10a511c | 2018-07-24 17:18:19 +0200 | [diff] [blame] | 21 | RCC_DDRITFCR_DDRPHYCEN | |
| 22 | RCC_DDRITFCR_DDRPHYCAPBEN | | ||||
| 23 | RCC_DDRITFCR_DDRCAPBEN); | ||||
| Yann Gautier | 0d21680 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 24 | |
| 25 | stm32mp1_clk_rcc_regs_unlock(); | ||||
| Yann Gautier | 10a511c | 2018-07-24 17:18:19 +0200 | [diff] [blame] | 26 | } |