blob: e9028ccdf2127811dc851ab390b64f453b87f2ed [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <stdio.h>
32#include <string.h>
33#include <assert.h>
34#include <arch_helpers.h>
35#include <console.h>
36#include <platform.h>
37#include <psci.h>
38#include <psci_private.h>
Achin Guptac8afc782013-11-25 18:45:02 +000039#include <runtime_svc.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010040
41/*******************************************************************************
42 * Arrays that contains information needs to resume a cpu's execution when woken
43 * out of suspend or off states. 'psci_ns_einfo_idx' keeps track of the next
Achin Guptaa59caa42013-12-05 14:21:04 +000044 * free index in the 'psci_ns_entry_info' & 'psci_suspend_context' arrays. Each
Achin Gupta4f6ad662013-10-25 09:08:21 +010045 * cpu is allocated a single entry in each array during startup.
46 ******************************************************************************/
Achin Guptaa59caa42013-12-05 14:21:04 +000047suspend_context psci_suspend_context[PSCI_NUM_AFFS];
Achin Gupta4f6ad662013-10-25 09:08:21 +010048ns_entry_info psci_ns_entry_info[PSCI_NUM_AFFS];
49unsigned int psci_ns_einfo_idx;
50
51/*******************************************************************************
52 * Grand array that holds the platform's topology information for state
53 * management of affinity instances. Each node (aff_map_node) in the array
54 * corresponds to an affinity instance e.g. cluster, cpu within an mpidr
55 ******************************************************************************/
56aff_map_node psci_aff_map[PSCI_NUM_AFFS]
57__attribute__ ((section("tzfw_coherent_mem")));
58
59/*******************************************************************************
60 * In a system, a certain number of affinity instances are present at an
61 * affinity level. The cumulative number of instances across all levels are
62 * stored in 'psci_aff_map'. The topology tree has been flattenned into this
63 * array. To retrieve nodes, information about the extents of each affinity
64 * level i.e. start index and end index needs to be present. 'psci_aff_limits'
65 * stores this information.
66 ******************************************************************************/
67aff_limits_node psci_aff_limits[MPIDR_MAX_AFFLVL + 1];
68
69/*******************************************************************************
70 * Pointer to functions exported by the platform to complete power mgmt. ops
71 ******************************************************************************/
72plat_pm_ops *psci_plat_pm_ops;
73
74/*******************************************************************************
Achin Guptaa45e3972013-12-05 15:10:48 +000075 * Routine to return the maximum affinity level to traverse to after a cpu has
76 * been physically powered up. It is expected to be called immediately after
77 * reset from assembler code. It has to find its 'aff_map_node' instead of
78 * getting it as an argument.
79 * TODO: Calling psci_get_aff_map_node() with the MMU disabled is slow. Add
80 * support to allow faster access to the target affinity level.
81 ******************************************************************************/
82int get_power_on_target_afflvl(unsigned long mpidr)
83{
84 aff_map_node *node;
85 unsigned int state;
86
87 /* Retrieve our node from the topology tree */
88 node = psci_get_aff_map_node(mpidr & MPIDR_AFFINITY_MASK, MPIDR_AFFLVL0);
89 assert(node);
90
91 /*
92 * Return the maximum supported affinity level if this cpu was off.
93 * Call the handler in the suspend code if this cpu had been suspended.
94 * Any other state is invalid.
95 */
96 state = psci_get_state(node->state);
97 if (state == PSCI_STATE_ON_PENDING)
98 return get_max_afflvl();
99
100 if (state == PSCI_STATE_SUSPEND)
101 return psci_get_suspend_afflvl(node);
102
103 return PSCI_E_INVALID_PARAMS;
104}
105
106/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100107 * Simple routine to retrieve the maximum affinity level supported by the
108 * platform and check that it makes sense.
109 ******************************************************************************/
110int get_max_afflvl()
111{
112 int aff_lvl;
113
114 aff_lvl = plat_get_max_afflvl();
115 assert(aff_lvl <= MPIDR_MAX_AFFLVL && aff_lvl >= MPIDR_AFFLVL0);
116
117 return aff_lvl;
118}
119
120/*******************************************************************************
121 * Simple routine to set the id of an affinity instance at a given level in the
122 * mpidr.
123 ******************************************************************************/
124unsigned long mpidr_set_aff_inst(unsigned long mpidr,
125 unsigned char aff_inst,
126 int aff_lvl)
127{
128 unsigned long aff_shift;
129
130 assert(aff_lvl <= MPIDR_AFFLVL3);
131
132 /*
133 * Decide the number of bits to shift by depending upon
134 * the affinity level
135 */
136 aff_shift = get_afflvl_shift(aff_lvl);
137
138 /* Clear the existing affinity instance & set the new one*/
139 mpidr &= ~(MPIDR_AFFLVL_MASK << aff_shift);
140 mpidr |= aff_inst << aff_shift;
141
142 return mpidr;
143}
144
145/*******************************************************************************
Achin Gupta0959db52013-12-02 17:33:04 +0000146 * This function sanity checks a range of affinity levels.
147 ******************************************************************************/
148int psci_check_afflvl_range(int start_afflvl, int end_afflvl)
149{
150 /* Sanity check the parameters passed */
151 if (end_afflvl > MPIDR_MAX_AFFLVL)
152 return PSCI_E_INVALID_PARAMS;
153
154 if (start_afflvl < MPIDR_AFFLVL0)
155 return PSCI_E_INVALID_PARAMS;
156
157 if (end_afflvl < start_afflvl)
158 return PSCI_E_INVALID_PARAMS;
159
160 return PSCI_E_SUCCESS;
161}
162
163/*******************************************************************************
164 * This function is passed an array of pointers to affinity level nodes in the
165 * topology tree for an mpidr. It picks up locks for each affinity level bottom
166 * up in the range specified.
167 ******************************************************************************/
168void psci_acquire_afflvl_locks(unsigned long mpidr,
169 int start_afflvl,
170 int end_afflvl,
171 mpidr_aff_map_nodes mpidr_nodes)
172{
173 int level;
174
175 for (level = start_afflvl; level <= end_afflvl; level++) {
176 if (mpidr_nodes[level] == NULL)
177 continue;
178 bakery_lock_get(mpidr, &mpidr_nodes[level]->lock);
179 }
180}
181
182/*******************************************************************************
183 * This function is passed an array of pointers to affinity level nodes in the
184 * topology tree for an mpidr. It releases the lock for each affinity level top
185 * down in the range specified.
186 ******************************************************************************/
187void psci_release_afflvl_locks(unsigned long mpidr,
188 int start_afflvl,
189 int end_afflvl,
190 mpidr_aff_map_nodes mpidr_nodes)
191{
192 int level;
193
194 for (level = end_afflvl; level >= start_afflvl; level--) {
195 if (mpidr_nodes[level] == NULL)
196 continue;
197 bakery_lock_release(mpidr, &mpidr_nodes[level]->lock);
198 }
199}
200
201/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100202 * Simple routine to determine whether an affinity instance at a given level
203 * in an mpidr exists or not.
204 ******************************************************************************/
205int psci_validate_mpidr(unsigned long mpidr, int level)
206{
207 aff_map_node *node;
208
209 node = psci_get_aff_map_node(mpidr, level);
210 if (node && (node->state & PSCI_AFF_PRESENT))
211 return PSCI_E_SUCCESS;
212 else
213 return PSCI_E_INVALID_PARAMS;
214}
215
216/*******************************************************************************
217 * Simple routine to determine the first affinity level instance that is present
218 * between the start and end affinity levels. This helps to skip handling of
219 * absent affinity levels while performing psci operations.
220 * The start level can be > or <= to the end level depending upon whether this
221 * routine is expected to search top down or bottom up.
222 ******************************************************************************/
223int psci_get_first_present_afflvl(unsigned long mpidr,
224 int start_afflvl,
225 int end_afflvl,
226 aff_map_node **node)
227{
228 int level;
229
230 /* Check whether we have to search up or down */
231 if (start_afflvl <= end_afflvl) {
232 for (level = start_afflvl; level <= end_afflvl; level++) {
233 *node = psci_get_aff_map_node(mpidr, level);
234 if (*node && ((*node)->state & PSCI_AFF_PRESENT))
235 break;
236 }
237 } else {
238 for (level = start_afflvl; level >= end_afflvl; level--) {
239 *node = psci_get_aff_map_node(mpidr, level);
240 if (*node && ((*node)->state & PSCI_AFF_PRESENT))
241 break;
242 }
243 }
244
245 return level;
246}
247
248/*******************************************************************************
Achin Gupta0959db52013-12-02 17:33:04 +0000249 * Iteratively change the affinity state between the current and target affinity
Achin Gupta4f6ad662013-10-25 09:08:21 +0100250 * levels. The target state matters only if we are starting from affinity level
251 * 0 i.e. a cpu otherwise the state depends upon the state of the lower affinity
252 * levels.
253 ******************************************************************************/
Achin Gupta0959db52013-12-02 17:33:04 +0000254int psci_change_state(mpidr_aff_map_nodes mpidr_nodes,
255 int start_afflvl,
256 int end_afflvl,
Achin Gupta4f6ad662013-10-25 09:08:21 +0100257 unsigned int tgt_state)
258{
Achin Gupta0959db52013-12-02 17:33:04 +0000259 int rc = PSCI_E_SUCCESS, level;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100260 unsigned int state;
Achin Gupta0959db52013-12-02 17:33:04 +0000261 aff_map_node *node;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100262
Achin Gupta0959db52013-12-02 17:33:04 +0000263 /*
264 * Get a temp pointer to the node. It is not possible that affinity
265 * level 0 is missing. Simply ignore higher missing levels.
266 */
267 for (level = start_afflvl; level <= end_afflvl; level++) {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100268
Achin Gupta0959db52013-12-02 17:33:04 +0000269 node = mpidr_nodes[level];
270 if (level == MPIDR_AFFLVL0) {
271 assert(node);
272 psci_set_state(node->state, tgt_state);
273 } else {
274 if (node == NULL)
275 continue;
276 state = psci_calculate_affinity_state(node);
277 psci_set_state(node->state, state);
278 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100279 }
280
Achin Gupta0959db52013-12-02 17:33:04 +0000281 /* If all went well then the cpu should be in the target state */
282 if (start_afflvl == MPIDR_AFFLVL0) {
283 node = mpidr_nodes[MPIDR_AFFLVL0];
284 state = psci_get_state(node->state);
285 assert(tgt_state == state);
286 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100287
288 return rc;
289}
290
291/*******************************************************************************
292 * This routine does the heavy lifting for psci_change_state(). It examines the
293 * state of each affinity instance at the next lower affinity level and decides
Achin Gupta3140a9e2013-12-02 16:23:12 +0000294 * its final state accordingly. If a lower affinity instance is ON then the
Achin Gupta4f6ad662013-10-25 09:08:21 +0100295 * higher affinity instance is ON. If all the lower affinity instances are OFF
296 * then the higher affinity instance is OFF. If atleast one lower affinity
297 * instance is SUSPENDED then the higher affinity instance is SUSPENDED. If only
298 * a single lower affinity instance is ON_PENDING then the higher affinity
299 * instance in ON_PENDING as well.
300 ******************************************************************************/
301unsigned int psci_calculate_affinity_state(aff_map_node *aff_node)
302{
303 int ctr;
304 unsigned int aff_count, hi_aff_state;
305 unsigned long tempidr;
306 aff_map_node *lo_aff_node;
307
Achin Gupta3140a9e2013-12-02 16:23:12 +0000308 /* Cannot calculate lowest affinity state. It is simply assigned */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100309 assert(aff_node->level > MPIDR_AFFLVL0);
310
311 /*
312 * Find the number of affinity instances at level X-1 e.g. number of
313 * cpus in a cluster. The level X state depends upon the state of each
314 * instance at level X-1
315 */
316 hi_aff_state = PSCI_STATE_OFF;
317 aff_count = plat_get_aff_count(aff_node->level - 1, aff_node->mpidr);
318 for (ctr = 0; ctr < aff_count; ctr++) {
319
320 /*
321 * Create a mpidr for each lower affinity level (X-1). Use their
322 * states to influence the higher affinity state (X).
323 */
324 tempidr = mpidr_set_aff_inst(aff_node->mpidr,
325 ctr,
326 aff_node->level - 1);
327 lo_aff_node = psci_get_aff_map_node(tempidr,
328 aff_node->level - 1);
329 assert(lo_aff_node);
330
331 /* Continue only if the cpu exists within the cluster */
332 if (!(lo_aff_node->state & PSCI_AFF_PRESENT))
333 continue;
334
335 switch (psci_get_state(lo_aff_node->state)) {
336
337 /*
338 * If any lower affinity is on within the cluster, then
339 * the higher affinity is on.
340 */
341 case PSCI_STATE_ON:
342 return PSCI_STATE_ON;
343
344 /*
345 * At least one X-1 needs to be suspended for X to be suspended
Achin Gupta3140a9e2013-12-02 16:23:12 +0000346 * but it is effectively on for the affinity_info call.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100347 * SUSPEND > ON_PENDING > OFF.
348 */
349 case PSCI_STATE_SUSPEND:
350 hi_aff_state = PSCI_STATE_SUSPEND;
351 continue;
352
353 /*
354 * Atleast one X-1 needs to be on_pending & the rest off for X
355 * to be on_pending. ON_PENDING > OFF.
356 */
357 case PSCI_STATE_ON_PENDING:
358 if (hi_aff_state != PSCI_STATE_SUSPEND)
359 hi_aff_state = PSCI_STATE_ON_PENDING;
360 continue;
361
362 /* Higher affinity is off if all lower affinities are off. */
363 case PSCI_STATE_OFF:
364 continue;
365
366 default:
367 assert(0);
368 }
369 }
370
371 return hi_aff_state;
372}
373
374/*******************************************************************************
375 * This function retrieves all the stashed information needed to correctly
376 * resume a cpu's execution in the non-secure state after it has been physically
377 * powered on i.e. turned ON or resumed from SUSPEND
378 ******************************************************************************/
Achin Guptac8afc782013-11-25 18:45:02 +0000379void psci_get_ns_entry_info(unsigned int index)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100380{
381 unsigned long sctlr = 0, scr, el_status, id_aa64pfr0;
Achin Guptac8afc782013-11-25 18:45:02 +0000382 gp_regs *ns_gp_regs;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100383
384 scr = read_scr();
385
386 /* Switch to the non-secure view of the registers */
387 write_scr(scr | SCR_NS_BIT);
388
389 /* Find out which EL we are going to */
390 id_aa64pfr0 = read_id_aa64pfr0_el1();
391 el_status = (id_aa64pfr0 >> ID_AA64PFR0_EL2_SHIFT) &
392 ID_AA64PFR0_ELX_MASK;
393
394 /* Restore endianess */
395 if (psci_ns_entry_info[index].sctlr & SCTLR_EE_BIT)
396 sctlr |= SCTLR_EE_BIT;
397 else
398 sctlr &= ~SCTLR_EE_BIT;
399
400 /* Turn off MMU and Caching */
401 sctlr &= ~(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_M_BIT);
402
403 /* Set the register width */
404 if (psci_ns_entry_info[index].scr & SCR_RW_BIT)
405 scr |= SCR_RW_BIT;
406 else
407 scr &= ~SCR_RW_BIT;
408
409 scr |= SCR_NS_BIT;
410
411 if (el_status)
412 write_sctlr_el2(sctlr);
413 else
414 write_sctlr_el1(sctlr);
415
416 /* Fulfill the cpu_on entry reqs. as per the psci spec */
417 write_scr(scr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100418 write_elr(psci_ns_entry_info[index].eret_info.entrypoint);
419
Achin Guptac8afc782013-11-25 18:45:02 +0000420 /*
421 * Set the general purpose registers to ~0 upon entry into the
422 * non-secure world except for x0 which should contain the
423 * context id & spsr. This is done directly on the "would be"
424 * stack pointer. Prior to entry into the non-secure world, an
425 * offset equivalent to the size of the 'gp_regs' structure is
426 * added to the sp. This general purpose register context is
427 * retrieved then.
428 */
429 ns_gp_regs = (gp_regs *) platform_get_stack(read_mpidr());
430 ns_gp_regs--;
431 memset(ns_gp_regs, ~0, sizeof(*ns_gp_regs));
432 ns_gp_regs->x0 = psci_ns_entry_info[index].context_id;
433 ns_gp_regs->spsr = psci_ns_entry_info[index].eret_info.spsr;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100434}
435
436/*******************************************************************************
437 * This function retrieves and stashes all the information needed to correctly
438 * resume a cpu's execution in the non-secure state after it has been physically
439 * powered on i.e. turned ON or resumed from SUSPEND. This is done prior to
440 * turning it on or before suspending it.
441 ******************************************************************************/
442int psci_set_ns_entry_info(unsigned int index,
443 unsigned long entrypoint,
444 unsigned long context_id)
445{
446 int rc = PSCI_E_SUCCESS;
447 unsigned int rw, mode, ee, spsr = 0;
448 unsigned long id_aa64pfr0 = read_id_aa64pfr0_el1(), scr = read_scr();
449 unsigned long el_status;
450
451 /* Figure out what mode do we enter the non-secure world in */
452 el_status = (id_aa64pfr0 >> ID_AA64PFR0_EL2_SHIFT) &
453 ID_AA64PFR0_ELX_MASK;
454
455 /*
456 * Figure out whether the cpu enters the non-secure address space
457 * in aarch32 or aarch64
458 */
459 rw = scr & SCR_RW_BIT;
460 if (rw) {
461
462 /*
463 * Check whether a Thumb entry point has been provided for an
464 * aarch64 EL
465 */
466 if (entrypoint & 0x1)
467 return PSCI_E_INVALID_PARAMS;
468
469 if (el_status && (scr & SCR_HCE_BIT)) {
470 mode = MODE_EL2;
471 ee = read_sctlr_el2() & SCTLR_EE_BIT;
472 } else {
473 mode = MODE_EL1;
474 ee = read_sctlr_el1() & SCTLR_EE_BIT;
475 }
476
477 spsr = DAIF_DBG_BIT | DAIF_ABT_BIT;
478 spsr |= DAIF_IRQ_BIT | DAIF_FIQ_BIT;
479 spsr <<= PSR_DAIF_SHIFT;
480 spsr |= make_spsr(mode, MODE_SP_ELX, !rw);
481
482 psci_ns_entry_info[index].sctlr |= ee;
483 psci_ns_entry_info[index].scr |= SCR_RW_BIT;
484 } else {
485
486 /* Check whether aarch32 has to be entered in Thumb mode */
487 if (entrypoint & 0x1)
488 spsr = SPSR32_T_BIT;
489
490 if (el_status && (scr & SCR_HCE_BIT)) {
491 mode = AARCH32_MODE_HYP;
492 ee = read_sctlr_el2() & SCTLR_EE_BIT;
493 } else {
494 mode = AARCH32_MODE_SVC;
495 ee = read_sctlr_el1() & SCTLR_EE_BIT;
496 }
497
498 /*
499 * TODO: Choose async. exception bits if HYP mode is not
500 * implemented according to the values of SCR.{AW, FW} bits
501 */
502 spsr |= DAIF_ABT_BIT | DAIF_IRQ_BIT | DAIF_FIQ_BIT;
503 spsr <<= PSR_DAIF_SHIFT;
504 if(ee)
505 spsr |= SPSR32_EE_BIT;
506 spsr |= mode;
507
508 /* Ensure that the CSPR.E and SCTLR.EE bits match */
509 psci_ns_entry_info[index].sctlr |= ee;
510 psci_ns_entry_info[index].scr &= ~SCR_RW_BIT;
511 }
512
513 psci_ns_entry_info[index].eret_info.entrypoint = entrypoint;
514 psci_ns_entry_info[index].eret_info.spsr = spsr;
515 psci_ns_entry_info[index].context_id = context_id;
516
517 return rc;
518}
519
520/*******************************************************************************
521 * An affinity level could be on, on_pending, suspended or off. These are the
Achin Gupta3140a9e2013-12-02 16:23:12 +0000522 * logical states it can be in. Physically either it is off or on. When it is in
523 * the state on_pending then it is about to be turned on. It is not possible to
Achin Gupta4f6ad662013-10-25 09:08:21 +0100524 * tell whether that's actually happenned or not. So we err on the side of
525 * caution & treat the affinity level as being turned off.
526 ******************************************************************************/
527inline unsigned int psci_get_phys_state(unsigned int aff_state)
528{
529 return (aff_state != PSCI_STATE_ON ? PSCI_STATE_OFF : PSCI_STATE_ON);
530}
531
532unsigned int psci_get_aff_phys_state(aff_map_node *aff_node)
533{
534 unsigned int aff_state;
535
536 aff_state = psci_get_state(aff_node->state);
537 return psci_get_phys_state(aff_state);
538}
539
540/*******************************************************************************
Achin Gupta0959db52013-12-02 17:33:04 +0000541 * This function takes an array of pointers to affinity instance nodes in the
542 * topology tree and calls the physical power on handler for the corresponding
543 * affinity levels
544 ******************************************************************************/
545static int psci_call_power_on_handlers(mpidr_aff_map_nodes mpidr_nodes,
546 int start_afflvl,
547 int end_afflvl,
548 afflvl_power_on_finisher *pon_handlers,
549 unsigned long mpidr)
550{
551 int rc = PSCI_E_INVALID_PARAMS, level;
552 aff_map_node *node;
553
554 for (level = end_afflvl; level >= start_afflvl; level--) {
555 node = mpidr_nodes[level];
556 if (node == NULL)
557 continue;
558
559 /*
560 * If we run into any trouble while powering up an
561 * affinity instance, then there is no recovery path
562 * so simply return an error and let the caller take
563 * care of the situation.
564 */
565 rc = pon_handlers[level](mpidr, node);
566 if (rc != PSCI_E_SUCCESS)
567 break;
568 }
569
570 return rc;
571}
572
573/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100574 * Generic handler which is called when a cpu is physically powered on. It
Achin Gupta0959db52013-12-02 17:33:04 +0000575 * traverses through all the affinity levels performing generic, architectural,
Achin Gupta4f6ad662013-10-25 09:08:21 +0100576 * platform setup and state management e.g. for a cluster that's been powered
577 * on, it will call the platform specific code which will enable coherency at
578 * the interconnect level. For a cpu it could mean turning on the MMU etc.
579 *
Achin Gupta0959db52013-12-02 17:33:04 +0000580 * The state of all the relevant affinity levels is changed after calling the
581 * affinity level specific handlers as their actions would depend upon the state
582 * the affinity level is exiting from.
583 *
584 * The affinity level specific handlers are called in descending order i.e. from
585 * the highest to the lowest affinity level implemented by the platform because
586 * to turn on affinity level X it is neccesary to turn on affinity level X + 1
587 * first.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100588 *
589 * CAUTION: This function is called with coherent stacks so that coherency and
590 * the mmu can be turned on safely.
591 ******************************************************************************/
Achin Gupta0959db52013-12-02 17:33:04 +0000592void psci_afflvl_power_on_finish(unsigned long mpidr,
593 int start_afflvl,
594 int end_afflvl,
595 afflvl_power_on_finisher *pon_handlers)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100596{
Achin Gupta0959db52013-12-02 17:33:04 +0000597 mpidr_aff_map_nodes mpidr_nodes;
598 int rc;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100599
600 mpidr &= MPIDR_AFFINITY_MASK;;
601
602 /*
Achin Gupta0959db52013-12-02 17:33:04 +0000603 * Collect the pointers to the nodes in the topology tree for
604 * each affinity instance in the mpidr. If this function does
605 * not return successfully then either the mpidr or the affinity
606 * levels are incorrect. Either case is an irrecoverable error.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100607 */
Achin Gupta0959db52013-12-02 17:33:04 +0000608 rc = psci_get_aff_map_nodes(mpidr,
609 start_afflvl,
610 end_afflvl,
611 mpidr_nodes);
612 assert (rc == PSCI_E_SUCCESS);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100613
614 /*
Achin Gupta0959db52013-12-02 17:33:04 +0000615 * This function acquires the lock corresponding to each affinity
616 * level so that by the time all locks are taken, the system topology
617 * is snapshot and state management can be done safely.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100618 */
Achin Gupta0959db52013-12-02 17:33:04 +0000619 psci_acquire_afflvl_locks(mpidr,
620 start_afflvl,
621 end_afflvl,
622 mpidr_nodes);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100623
624 /* Perform generic, architecture and platform specific handling */
Achin Gupta0959db52013-12-02 17:33:04 +0000625 rc = psci_call_power_on_handlers(mpidr_nodes,
626 start_afflvl,
627 end_afflvl,
628 pon_handlers,
629 mpidr);
630 assert (rc == PSCI_E_SUCCESS);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100631
632 /*
Achin Gupta0959db52013-12-02 17:33:04 +0000633 * State management: Update the state of each affinity instance
634 * between the start and end affinity levels
Achin Gupta4f6ad662013-10-25 09:08:21 +0100635 */
Achin Gupta0959db52013-12-02 17:33:04 +0000636 psci_change_state(mpidr_nodes,
637 start_afflvl,
638 end_afflvl,
639 PSCI_STATE_ON);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100640
Achin Gupta0959db52013-12-02 17:33:04 +0000641 /*
642 * This loop releases the lock corresponding to each affinity level
643 * in the reverse order to which they were acquired.
644 */
645 psci_release_afflvl_locks(mpidr,
646 start_afflvl,
647 end_afflvl,
648 mpidr_nodes);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100649}