Antonio Nino Diaz | f3ff9f7 | 2018-09-18 01:36:00 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch_helpers.h> |
| 8 | #include <assert.h> |
| 9 | #include <console.h> |
| 10 | #include <debug.h> |
| 11 | #include <errno.h> |
| 12 | #include <gicv2.h> |
| 13 | #include <mmio.h> |
| 14 | #include <platform.h> |
| 15 | #include <platform_def.h> |
| 16 | #include <psci.h> |
| 17 | |
| 18 | #include "gxbb_private.h" |
| 19 | |
| 20 | #define SCPI_POWER_ON 0 |
| 21 | #define SCPI_POWER_RETENTION 1 |
| 22 | #define SCPI_POWER_OFF 3 |
| 23 | |
| 24 | #define SCPI_SYSTEM_SHUTDOWN 0 |
| 25 | #define SCPI_SYSTEM_REBOOT 1 |
| 26 | |
| 27 | static uintptr_t gxbb_sec_entrypoint; |
| 28 | |
| 29 | static void gxbb_program_mailbox(u_register_t mpidr, uint64_t value) |
| 30 | { |
| 31 | unsigned int core = plat_gxbb_calc_core_pos(mpidr); |
| 32 | uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4); |
| 33 | |
| 34 | mmio_write_64(cpu_mailbox_addr, value); |
| 35 | flush_dcache_range(cpu_mailbox_addr, sizeof(uint64_t)); |
| 36 | } |
| 37 | |
| 38 | static void __dead2 gxbb_system_reset(void) |
| 39 | { |
| 40 | INFO("BL31: PSCI_SYSTEM_RESET\n"); |
| 41 | |
| 42 | uint32_t status = mmio_read_32(GXBB_AO_RTI_STATUS_REG3); |
| 43 | |
| 44 | NOTICE("BL31: Reboot reason: 0x%x\n", status); |
| 45 | |
| 46 | status &= 0xFFFF0FF0; |
| 47 | |
| 48 | console_flush(); |
| 49 | |
| 50 | mmio_write_32(GXBB_AO_RTI_STATUS_REG3, status); |
| 51 | |
| 52 | int ret = scpi_sys_power_state(SCPI_SYSTEM_REBOOT); |
| 53 | |
| 54 | if (ret != 0) { |
| 55 | ERROR("BL31: PSCI_SYSTEM_RESET: SCP error: %u\n", ret); |
| 56 | panic(); |
| 57 | } |
| 58 | |
| 59 | wfi(); |
| 60 | |
| 61 | ERROR("BL31: PSCI_SYSTEM_RESET: Operation not handled\n"); |
| 62 | panic(); |
| 63 | } |
| 64 | |
| 65 | static void __dead2 gxbb_system_off(void) |
| 66 | { |
| 67 | INFO("BL31: PSCI_SYSTEM_OFF\n"); |
| 68 | |
| 69 | unsigned int ret = scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN); |
| 70 | |
| 71 | if (ret != 0) { |
| 72 | ERROR("BL31: PSCI_SYSTEM_OFF: SCP error %u\n", ret); |
| 73 | panic(); |
| 74 | } |
| 75 | |
| 76 | gxbb_program_mailbox(read_mpidr_el1(), 0); |
| 77 | |
| 78 | wfi(); |
| 79 | |
| 80 | ERROR("BL31: PSCI_SYSTEM_OFF: Operation not handled\n"); |
| 81 | panic(); |
| 82 | } |
| 83 | |
| 84 | static int32_t gxbb_pwr_domain_on(u_register_t mpidr) |
| 85 | { |
| 86 | gxbb_program_mailbox(mpidr, gxbb_sec_entrypoint); |
| 87 | scpi_set_css_power_state(mpidr, |
| 88 | SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON); |
| 89 | dmbsy(); |
| 90 | sev(); |
| 91 | |
| 92 | return PSCI_E_SUCCESS; |
| 93 | } |
| 94 | |
| 95 | static void gxbb_pwr_domain_on_finish(const psci_power_state_t *target_state) |
| 96 | { |
| 97 | assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == |
| 98 | PLAT_LOCAL_STATE_OFF); |
| 99 | |
| 100 | gicv2_pcpu_distif_init(); |
| 101 | gicv2_cpuif_enable(); |
| 102 | } |
| 103 | |
| 104 | /******************************************************************************* |
| 105 | * Platform handlers and setup function. |
| 106 | ******************************************************************************/ |
| 107 | static const plat_psci_ops_t gxbb_ops = { |
| 108 | .pwr_domain_on = gxbb_pwr_domain_on, |
| 109 | .pwr_domain_on_finish = gxbb_pwr_domain_on_finish, |
| 110 | .system_off = gxbb_system_off, |
| 111 | .system_reset = gxbb_system_reset, |
| 112 | }; |
| 113 | |
| 114 | int plat_setup_psci_ops(uintptr_t sec_entrypoint, |
| 115 | const plat_psci_ops_t **psci_ops) |
| 116 | { |
| 117 | gxbb_sec_entrypoint = sec_entrypoint; |
| 118 | *psci_ops = &gxbb_ops; |
| 119 | return 0; |
| 120 | } |