Add files to eliminate HAL dependency, build/compile pass
Signed-off-by: Bohdan Kovalchuk <bohd@cypress.com>
Signed-off-by: Roman Okhrimenko <roman.okhrimenko@cypress.com>
diff --git a/boot/cypress/platforms/cycfg_peripherals.c b/boot/cypress/platforms/cycfg_peripherals.c
new file mode 100644
index 0000000..1c55938
--- /dev/null
+++ b/boot/cypress/platforms/cycfg_peripherals.c
@@ -0,0 +1,73 @@
+/*******************************************************************************
+* File Name: cycfg_peripherals.c
+*
+* Description:
+* Peripheral Hardware Block configuration
+* This file was automatically generated and should not be modified.
+* Device Configurator: 2.0.0.1483
+* Device Support Library (../../../psoc6pdl): 1.3.1.1499
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_peripherals.h"
+
+const cy_stc_scb_uart_config_t CYBSP_UART_config =
+{
+ .uartMode = CY_SCB_UART_STANDARD,
+ .enableMutliProcessorMode = false,
+ .smartCardRetryOnNack = false,
+ .irdaInvertRx = false,
+ .irdaEnableLowPowerReceiver = false,
+ .oversample = 8,
+ .enableMsbFirst = false,
+ .dataWidth = 8UL,
+ .parity = CY_SCB_UART_PARITY_NONE,
+ .stopBits = CY_SCB_UART_STOP_BITS_1,
+ .enableInputFilter = false,
+ .breakWidth = 11UL,
+ .dropOnFrameError = false,
+ .dropOnParityError = false,
+ .receiverAddress = 0x0UL,
+ .receiverAddressMask = 0x0UL,
+ .acceptAddrInFifo = false,
+ .enableCts = false,
+ .ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
+ .rtsRxFifoLevel = 0UL,
+ .rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
+ .rxFifoTriggerLevel = 0UL,
+ .rxFifoIntEnableMask = 0UL,
+ .txFifoTriggerLevel = 63UL,
+ .txFifoIntEnableMask = 0UL,
+};
+#if defined (CY_USING_HAL)
+ const cyhal_resource_inst_t CYBSP_UART_obj =
+ {
+ .type = CYHAL_RSC_SCB,
+ .block_num = 5U,
+ .channel_num = 0U,
+ };
+#endif //defined (CY_USING_HAL)
+
+
+void init_cycfg_peripherals(void)
+{
+ Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_16_BIT, 0U);
+#if defined (CY_USING_HAL)
+ cyhal_hwmgr_reserve(&CYBSP_UART_obj);
+#endif //defined (CY_USING_HAL)
+}
diff --git a/boot/cypress/platforms/cycfg_peripherals.h b/boot/cypress/platforms/cycfg_peripherals.h
new file mode 100644
index 0000000..41a0383
--- /dev/null
+++ b/boot/cypress/platforms/cycfg_peripherals.h
@@ -0,0 +1,57 @@
+/*******************************************************************************
+* File Name: cycfg_peripherals.h
+*
+* Description:
+* Peripheral Hardware Block configuration
+* This file was automatically generated and should not be modified.
+* Device Configurator: 2.0.0.1483
+* Device Support Library (../../../psoc6pdl): 1.3.1.1499
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_PERIPHERALS_H)
+#define CYCFG_PERIPHERALS_H
+
+// #include "cycfg_notices.h"
+#include "cy_scb_uart.h"
+#include "cy_sysclk.h"
+#if defined (CY_USING_HAL)
+ #include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define CYBSP_UART_ENABLED 1U
+#define CYBSP_UART_HW SCB5
+#define CYBSP_UART_IRQ scb_5_interrupt_IRQn
+
+extern const cy_stc_scb_uart_config_t CYBSP_UART_config;
+#if defined (CY_USING_HAL)
+ extern const cyhal_resource_inst_t CYBSP_UART_obj;
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_peripherals(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_PERIPHERALS_H */
diff --git a/boot/cypress/platforms/cycfg_pins.c b/boot/cypress/platforms/cycfg_pins.c
new file mode 100644
index 0000000..771d772
--- /dev/null
+++ b/boot/cypress/platforms/cycfg_pins.c
@@ -0,0 +1,89 @@
+/*******************************************************************************
+* File Name: cycfg_pins.c
+*
+* Description:
+* Pin configuration
+* This file was automatically generated and should not be modified.
+* Device Configurator: 2.0.0.1483
+* Device Support Library (../../../psoc6pdl): 1.3.1.1499
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_pins.h"
+
+const cy_stc_gpio_pin_config_t CYBSP_UART_RX_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_HIGHZ,
+ .hsiom = CYBSP_UART_RX_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+ const cyhal_resource_inst_t CYBSP_UART_RX_obj =
+ {
+ .type = CYHAL_RSC_GPIO,
+ .block_num = CYBSP_UART_RX_PORT_NUM,
+ .channel_num = CYBSP_UART_RX_PIN,
+ };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_UART_TX_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+ .hsiom = CYBSP_UART_TX_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+ const cyhal_resource_inst_t CYBSP_UART_TX_obj =
+ {
+ .type = CYHAL_RSC_GPIO,
+ .block_num = CYBSP_UART_TX_PORT_NUM,
+ .channel_num = CYBSP_UART_TX_PIN,
+ };
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_pins(void)
+{
+ Cy_GPIO_Pin_Init(CYBSP_UART_RX_PORT, CYBSP_UART_RX_PIN, &CYBSP_UART_RX_config);
+#if defined (CY_USING_HAL)
+ cyhal_hwmgr_reserve(&CYBSP_UART_RX_obj);
+#endif //defined (CY_USING_HAL)
+
+ Cy_GPIO_Pin_Init(CYBSP_UART_TX_PORT, CYBSP_UART_TX_PIN, &CYBSP_UART_TX_config);
+#if defined (CY_USING_HAL)
+ cyhal_hwmgr_reserve(&CYBSP_UART_TX_obj);
+#endif //defined (CY_USING_HAL)
+}
diff --git a/boot/cypress/platforms/cycfg_pins.h b/boot/cypress/platforms/cycfg_pins.h
new file mode 100644
index 0000000..c214826
--- /dev/null
+++ b/boot/cypress/platforms/cycfg_pins.h
@@ -0,0 +1,113 @@
+/*******************************************************************************
+* File Name: cycfg_pins.h
+*
+* Description:
+* Pin configuration
+* This file was automatically generated and should not be modified.
+* Device Configurator: 2.0.0.1483
+* Device Support Library (../../../psoc6pdl): 1.3.1.1499
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_PINS_H)
+#define CYCFG_PINS_H
+
+#include "cy_gpio.h"
+#if defined (CY_USING_HAL)
+ #include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+#include "cycfg_routing.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define CYBSP_UART_RX_ENABLED 1U
+#define CYBSP_UART_RX_PORT GPIO_PRT5
+#define CYBSP_UART_RX_PORT_NUM 5U
+#define CYBSP_UART_RX_PIN 0U
+#define CYBSP_UART_RX_NUM 0U
+#define CYBSP_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_UART_RX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_5_pin_0_HSIOM
+ #define ioss_0_port_5_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_UART_RX_HSIOM ioss_0_port_5_pin_0_HSIOM
+#define CYBSP_UART_RX_IRQ ioss_interrupts_gpio_5_IRQn
+#if defined (CY_USING_HAL)
+ #define CYBSP_UART_RX_HAL_PORT_PIN P5_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+ #define CYBSP_UART_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+ #define CYBSP_UART_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+ #define CYBSP_UART_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_UART_TX_ENABLED 1U
+#define CYBSP_UART_TX_PORT GPIO_PRT5
+#define CYBSP_UART_TX_PORT_NUM 5U
+#define CYBSP_UART_TX_PIN 1U
+#define CYBSP_UART_TX_NUM 1U
+#define CYBSP_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_UART_TX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_5_pin_1_HSIOM
+ #define ioss_0_port_5_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM
+#define CYBSP_UART_TX_IRQ ioss_interrupts_gpio_5_IRQn
+#if defined (CY_USING_HAL)
+ #define CYBSP_UART_TX_HAL_PORT_PIN P5_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+ #define CYBSP_UART_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+ #define CYBSP_UART_TX_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+ #define CYBSP_UART_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
+#if defined (CY_USING_HAL)
+ extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
+#if defined (CY_USING_HAL)
+ extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_UART_RX_config;
+#if defined (CY_USING_HAL)
+ extern const cyhal_resource_inst_t CYBSP_UART_RX_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_UART_TX_config;
+#if defined (CY_USING_HAL)
+ extern const cyhal_resource_inst_t CYBSP_UART_TX_obj;
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_pins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_PINS_H */
diff --git a/boot/cypress/platforms/cycfg_routing.c b/boot/cypress/platforms/cycfg_routing.c
new file mode 100644
index 0000000..063e736
--- /dev/null
+++ b/boot/cypress/platforms/cycfg_routing.c
@@ -0,0 +1,31 @@
+/*******************************************************************************
+* File Name: cycfg_routing.c
+*
+* Description:
+* Establishes all necessary connections between hardware elements.
+* This file was automatically generated and should not be modified.
+* Device Configurator: 2.0.0.1483
+* Device Support Library (../../../psoc6pdl): 1.4.0.1889
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_routing.h"
+
+void init_cycfg_routing(void)
+{
+}
diff --git a/boot/cypress/platforms/cycfg_routing.h b/boot/cypress/platforms/cycfg_routing.h
new file mode 100644
index 0000000..bfb2998
--- /dev/null
+++ b/boot/cypress/platforms/cycfg_routing.h
@@ -0,0 +1,46 @@
+/*******************************************************************************
+* File Name: cycfg_routing.h
+*
+* Description:
+* Establishes all necessary connections between hardware elements.
+* This file was automatically generated and should not be modified.
+* Device Configurator: 2.0.0.1483
+* Device Support Library (../../../psoc6pdl): 1.4.0.1889
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_ROUTING_H)
+#define CYCFG_ROUTING_H
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+void init_cycfg_routing(void);
+
+#define init_cycfg_connectivity() init_cycfg_routing()
+
+#define ioss_0_port_5_pin_0_HSIOM P5_0_SCB5_UART_RX
+#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_ROUTING_H */