TrustedFirmware Git Browser
Code Review Sign In
review.trustedfirmware.org / mirror / mcuboot / 89ecdac3b8fadebeef2647f0a96372d0b0f90abc / . / boot / cypress / platforms / cycfg_system.c
blob: 57ab01378e24144ad88c6af6253f8ee16ecd906e [file] [log] [blame]
Roman Okhrimenko89ecdac2020-02-28 17:05:55 +0200[diff] [blame^]1/*******************************************************************************
2* File Name: cycfg_system.c
3*
4* Description:
5* System configuration
6* This file was automatically generated and should not be modified.
7* Device Configurator: 2.0.0.1483
8* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.5.0.1837
9*
10********************************************************************************
11* Copyright 2017-2019 Cypress Semiconductor Corporation
12* SPDX-License-Identifier: Apache-2.0
13*
14* Licensed under the Apache License, Version 2.0 (the "License");
15* you may not use this file except in compliance with the License.
16* You may obtain a copy of the License at
17*
18* http://www.apache.org/licenses/LICENSE-2.0
19*
20* Unless required by applicable law or agreed to in writing, software
21* distributed under the License is distributed on an "AS IS" BASIS,
22* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23* See the License for the specific language governing permissions and
24* limitations under the License.
25********************************************************************************/
26
27#include "cycfg_system.h"
28
29#define CY_CFG_SYSCLK_ECO_ERROR 1
30#define CY_CFG_SYSCLK_ALTHF_ERROR 2
31#define CY_CFG_SYSCLK_PLL_ERROR 3
32#define CY_CFG_SYSCLK_FLL_ERROR 4
33#define CY_CFG_SYSCLK_WCO_ERROR 5
34#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1
35#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
36#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
37#define CY_CFG_SYSCLK_FLL_ENABLED 1
38#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
39#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL
40#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
41#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1
42#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL
43#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
44#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1
45#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 100UL
46#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
47#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1
48#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL
49#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
50#define CY_CFG_SYSCLK_ILO_ENABLED 1
51#define CY_CFG_SYSCLK_IMO_ENABLED 1
52#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
53#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
54#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
55#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1
56#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
57#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1
58#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
59#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
60#define CY_CFG_SYSCLK_PLL0_ENABLED 1
61#define CY_CFG_SYSCLK_PLL1_ENABLED 1
62#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
63#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
64#define CY_CFG_SYSCLK_WCO_ENABLED 1
65
66static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
67{
68 .fllMult = 500U,
69 .refDiv = 20U,
70 .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
71 .enableOutputDiv = true,
72 .lockTolerance = 10U,
73 .igain = 9U,
74 .pgain = 5U,
75 .settlingCount = 8U,
76 .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
77 .cco_Freq = 355U,
78};
79#if defined (CY_USING_HAL)
80 const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
81 {
82 .type = CYHAL_RSC_CLKPATH,
83 .block_num = 0U,
84 .channel_num = 0U,
85 };
86#endif //defined (CY_USING_HAL)
87#if defined (CY_USING_HAL)
88 const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
89 {
90 .type = CYHAL_RSC_CLKPATH,
91 .block_num = 1U,
92 .channel_num = 0U,
93 };
94#endif //defined (CY_USING_HAL)
95#if defined (CY_USING_HAL)
96 const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
97 {
98 .type = CYHAL_RSC_CLKPATH,
99 .block_num = 2U,
100 .channel_num = 0U,
101 };
102#endif //defined (CY_USING_HAL)
103static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
104{
105 .feedbackDiv = 36,
106 .referenceDiv = 1,
107 .outputDiv = 2,
108 .lfMode = false,
109 .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
110};
111static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig =
112{
113 .feedbackDiv = 30,
114 .referenceDiv = 1,
115 .outputDiv = 5,
116 .lfMode = false,
117 .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
118};
119
120__WEAK void cycfg_ClockStartupError(uint32_t error)
121{
122 (void)error; /* Suppress the compiler warning */
123 while(1);
124}
125__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit()
126{
127 Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_LF);
128}
129__STATIC_INLINE void Cy_SysClk_ClkBakInit()
130{
131 Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF);
132}
133__STATIC_INLINE void Cy_SysClk_ClkFastInit()
134{
135 Cy_SysClk_ClkFastSetDivider(0U);
136}
137__STATIC_INLINE void Cy_SysClk_FllInit()
138{
139 if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig))
140 {
141 cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
142 }
143 if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL))
144 {
145 cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
146 }
147}
148__STATIC_INLINE void Cy_SysClk_ClkHf0Init()
149{
150 Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH);
151 Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
152}
153__STATIC_INLINE void Cy_SysClk_ClkHf2Init()
154{
155 Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
156 Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
157 Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
158}
159__STATIC_INLINE void Cy_SysClk_ClkHf3Init()
160{
161 Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
162 Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE);
163 Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3);
164}
165__STATIC_INLINE void Cy_SysClk_ClkHf4Init()
166{
167 Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH);
168 Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_NO_DIVIDE);
169 Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4);
170}
171__STATIC_INLINE void Cy_SysClk_IloInit()
172{
173 /* The WDT is unlocked in the default startup code */
174 Cy_SysClk_IloEnable();
175 Cy_SysClk_IloHibernateOn(true);
176}
177__STATIC_INLINE void Cy_SysClk_ClkLfInit()
178{
179 /* The WDT is unlocked in the default startup code */
180 Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO);
181}
182__STATIC_INLINE void Cy_SysClk_ClkPath0Init()
183{
184 Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE);
185}
186__STATIC_INLINE void Cy_SysClk_ClkPath1Init()
187{
188 Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE);
189}
190__STATIC_INLINE void Cy_SysClk_ClkPath2Init()
191{
192 Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE);
193}
194__STATIC_INLINE void Cy_SysClk_ClkPeriInit()
195{
196 Cy_SysClk_ClkPeriSetDivider(1U);
197}
198__STATIC_INLINE void Cy_SysClk_Pll0Init()
199{
200 if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig))
201 {
202 cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
203 }
204 if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u))
205 {
206 cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
207 }
208}
209__STATIC_INLINE void Cy_SysClk_Pll1Init()
210{
211 if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(2U, &srss_0_clock_0_pll_1_pllConfig))
212 {
213 cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
214 }
215 if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(2U, 10000u))
216 {
217 cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
218 }
219}
220__STATIC_INLINE void Cy_SysClk_ClkSlowInit()
221{
222 Cy_SysClk_ClkSlowSetDivider(0U);
223}
224__STATIC_INLINE void Cy_SysClk_ClkTimerInit()
225{
226 Cy_SysClk_ClkTimerDisable();
227 Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO);
228 Cy_SysClk_ClkTimerSetDivider(0U);
229 Cy_SysClk_ClkTimerEnable();
230}
231__STATIC_INLINE void Cy_SysClk_WcoInit()
232{
233 (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
234 (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
235 if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL))
236 {
237 cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
238 }
239}
240
241
242void init_cycfg_system(void)
243{
244 /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
245 Cy_SysLib_SetWaitStates(false, 150UL);
246 #ifdef CY_CFG_PWR_ENABLED
247 #ifdef CY_CFG_PWR_INIT
248 init_cycfg_power();
249 #else
250 #warning Power system will not be configured. Update power personality to v1.20 or later.
251 #endif /* CY_CFG_PWR_INIT */
252 #endif /* CY_CFG_PWR_ENABLED */
253
254 /* Reset the core clock path to default and disable all the FLLs/PLLs */
255 Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
256 Cy_SysClk_ClkFastSetDivider(0U);
257 Cy_SysClk_ClkPeriSetDivider(1U);
258 Cy_SysClk_ClkSlowSetDivider(0U);
259 for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */
260 {
261 (void)Cy_SysClk_PllDisable(pll);
262 }
263 Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
264
265 if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
266 (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0)))
267 {
268 Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1);
269 }
270
271 Cy_SysClk_FllDisable();
272 Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO);
273 Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);
274 #ifdef CY_IP_MXBLESS
275 (void)Cy_BLE_EcoReset();
276 #endif
277
278
279 /* Enable all source clocks */
280 #ifdef CY_CFG_SYSCLK_PILO_ENABLED
281 Cy_SysClk_PiloInit();
282 #endif
283
284 #ifdef CY_CFG_SYSCLK_WCO_ENABLED
285 Cy_SysClk_WcoInit();
286 #endif
287
288 #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
289 Cy_SysClk_ClkLfInit();
290 #endif
291
292 #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
293 Cy_SysClk_AltHfInit();
294 #endif
295
296 #ifdef CY_CFG_SYSCLK_ECO_ENABLED
297 Cy_SysClk_EcoInit();
298 #endif
299
300 #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
301 Cy_SysClk_ExtClkInit();
302 #endif
303
304 /* Configure CPU clock dividers */
305 #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
306 Cy_SysClk_ClkFastInit();
307 #endif
308
309 #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
310 Cy_SysClk_ClkPeriInit();
311 #endif
312
313 #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
314 Cy_SysClk_ClkSlowInit();
315 #endif
316
317 #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
318 /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */
319 Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
320 Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
321 #else
322 #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
323 Cy_SysClk_ClkPath1Init();
324 #endif
325 #endif
326
327 /* Configure Path Clocks */
328 #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
329 Cy_SysClk_ClkPath0Init();
330 #endif
331 #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
332 Cy_SysClk_ClkPath2Init();
333 #endif
334 #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
335 Cy_SysClk_ClkPath3Init();
336 #endif
337 #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
338 Cy_SysClk_ClkPath4Init();
339 #endif
340 #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
341 Cy_SysClk_ClkPath5Init();
342 #endif
343 #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED
344 Cy_SysClk_ClkPath6Init();
345 #endif
346 #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED
347 Cy_SysClk_ClkPath7Init();
348 #endif
349 #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED
350 Cy_SysClk_ClkPath8Init();
351 #endif
352 #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED
353 Cy_SysClk_ClkPath9Init();
354 #endif
355 #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED
356 Cy_SysClk_ClkPath10Init();
357 #endif
358 #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED
359 Cy_SysClk_ClkPath11Init();
360 #endif
361 #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED
362 Cy_SysClk_ClkPath12Init();
363 #endif
364 #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED
365 Cy_SysClk_ClkPath13Init();
366 #endif
367 #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED
368 Cy_SysClk_ClkPath14Init();
369 #endif
370 #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
371 Cy_SysClk_ClkPath15Init();
372 #endif
373
374 /* Configure and enable FLL */
375 #ifdef CY_CFG_SYSCLK_FLL_ENABLED
376 Cy_SysClk_FllInit();
377 #endif
378
379 Cy_SysClk_ClkHf0Init();
380
381 #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
382 #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
383 /* Apply the ClkPath1 user setting */
384 Cy_SysClk_ClkPath1Init();
385 #endif
386 #endif
387
388 /* Configure and enable PLLs */
389 #ifdef CY_CFG_SYSCLK_PLL0_ENABLED
390 Cy_SysClk_Pll0Init();
391 #endif
392 #ifdef CY_CFG_SYSCLK_PLL1_ENABLED
393 Cy_SysClk_Pll1Init();
394 #endif
395 #ifdef CY_CFG_SYSCLK_PLL2_ENABLED
396 Cy_SysClk_Pll2Init();
397 #endif
398 #ifdef CY_CFG_SYSCLK_PLL3_ENABLED
399 Cy_SysClk_Pll3Init();
400 #endif
401 #ifdef CY_CFG_SYSCLK_PLL4_ENABLED
402 Cy_SysClk_Pll4Init();
403 #endif
404 #ifdef CY_CFG_SYSCLK_PLL5_ENABLED
405 Cy_SysClk_Pll5Init();
406 #endif
407 #ifdef CY_CFG_SYSCLK_PLL6_ENABLED
408 Cy_SysClk_Pll6Init();
409 #endif
410 #ifdef CY_CFG_SYSCLK_PLL7_ENABLED
411 Cy_SysClk_Pll7Init();
412 #endif
413 #ifdef CY_CFG_SYSCLK_PLL8_ENABLED
414 Cy_SysClk_Pll8Init();
415 #endif
416 #ifdef CY_CFG_SYSCLK_PLL9_ENABLED
417 Cy_SysClk_Pll9Init();
418 #endif
419 #ifdef CY_CFG_SYSCLK_PLL10_ENABLED
420 Cy_SysClk_Pll10Init();
421 #endif
422 #ifdef CY_CFG_SYSCLK_PLL11_ENABLED
423 Cy_SysClk_Pll11Init();
424 #endif
425 #ifdef CY_CFG_SYSCLK_PLL12_ENABLED
426 Cy_SysClk_Pll12Init();
427 #endif
428 #ifdef CY_CFG_SYSCLK_PLL13_ENABLED
429 Cy_SysClk_Pll13Init();
430 #endif
431 #ifdef CY_CFG_SYSCLK_PLL14_ENABLED
432 Cy_SysClk_Pll14Init();
433 #endif
434
435 /* Configure HF clocks */
436 #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
437 Cy_SysClk_ClkHf1Init();
438 #endif
439 #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
440 Cy_SysClk_ClkHf2Init();
441 #endif
442 #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
443 Cy_SysClk_ClkHf3Init();
444 #endif
445 #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
446 Cy_SysClk_ClkHf4Init();
447 #endif
448 #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
449 Cy_SysClk_ClkHf5Init();
450 #endif
451 #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED
452 Cy_SysClk_ClkHf6Init();
453 #endif
454 #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED
455 Cy_SysClk_ClkHf7Init();
456 #endif
457 #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED
458 Cy_SysClk_ClkHf8Init();
459 #endif
460 #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED
461 Cy_SysClk_ClkHf9Init();
462 #endif
463 #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED
464 Cy_SysClk_ClkHf10Init();
465 #endif
466 #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED
467 Cy_SysClk_ClkHf11Init();
468 #endif
469 #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED
470 Cy_SysClk_ClkHf12Init();
471 #endif
472 #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED
473 Cy_SysClk_ClkHf13Init();
474 #endif
475 #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED
476 Cy_SysClk_ClkHf14Init();
477 #endif
478 #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
479 Cy_SysClk_ClkHf15Init();
480 #endif
481
482 /* Configure miscellaneous clocks */
483 #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
484 Cy_SysClk_ClkTimerInit();
485 #endif
486
487 #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
488 Cy_SysClk_ClkAltSysTickInit();
489 #endif
490
491 #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
492 Cy_SysClk_ClkPumpInit();
493 #endif
494
495 #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
496 Cy_SysClk_ClkBakInit();
497 #endif
498
499 /* Configure default enabled clocks */
500 #ifdef CY_CFG_SYSCLK_ILO_ENABLED
501 Cy_SysClk_IloInit();
502 #else
503 Cy_SysClk_IloDisable();
504 #endif
505
506 #ifndef CY_CFG_SYSCLK_IMO_ENABLED
507 #error the IMO must be enabled for proper chip operation
508 #endif
509
510 #ifdef CY_CFG_SYSCLK_MFO_ENABLED
511 Cy_SysClk_MfoInit();
512 #endif
513
514 #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
515 Cy_SysClk_ClkMfInit();
516 #endif
517
518 /* Set accurate flash wait states */
519 #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
520 Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
521 #endif
522
523 /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
524 SystemCoreClockUpdate();
525
526#if defined (CY_USING_HAL)
527 cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
528#endif //defined (CY_USING_HAL)
529
530#if defined (CY_USING_HAL)
531 cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
532#endif //defined (CY_USING_HAL)
533
534#if defined (CY_USING_HAL)
535 cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
536#endif //defined (CY_USING_HAL)
537}