fix(cpus): workaround for Cortex-A720-AE erratum 3699562
Cortex-A720-AE erratum 3699562 that applies to r0p0 and is still
Open.
The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-3090091/latest/
Change-Id: Ib830470747822cac916750c01684a65cb5efc15b
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c
index e5d14d5..a6be68a 100644
--- a/lib/cpus/errata_common.c
+++ b/lib/cpus/errata_common.c
@@ -13,6 +13,7 @@
#include <cortex_a710.h>
#include <cortex_a715.h>
#include <cortex_a720.h>
+#include <cortex_a720_ae.h>
#include <cortex_x4.h>
#include <lib/cpus/cpu_ops.h>
#include <lib/cpus/errata.h>
@@ -68,6 +69,13 @@
break;
#endif /* ERRATA_A720_3699561 */
+#if ERRATA_A720_AE_3699562
+ case EXTRACT_PARTNUM(CORTEX_A720_AE_MIDR):
+ if (check_erratum_cortex_a720_ae_3699562(cpu_get_rev_var()) == ERRATA_APPLIES)
+ return true;
+ break;
+#endif /* ERRATA_A720_AE_3699562 */
+
default:
break;
}