Zelalem Aweke | 1839012 | 2021-07-13 14:05:20 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef GPT_DEFS_H |
| 8 | #define GPT_DEFS_H |
| 9 | |
| 10 | #include <arch.h> |
| 11 | #include <lib/utils_def.h> |
| 12 | |
| 13 | #include "gpt.h" |
| 14 | |
| 15 | /* GPI values */ |
| 16 | #define GPI_NO_ACCESS U(0x0) |
| 17 | #define GPI_SECURE U(0x8) |
| 18 | #define GPI_NS U(0x9) |
| 19 | #define GPI_ROOT U(0xa) |
| 20 | #define GPI_REALM U(0xb) |
| 21 | #define GPI_ANY U(0xf) |
| 22 | #define GPI_VAL_MASK ULL(0xf) |
| 23 | |
| 24 | /* GPT descriptor bit definitions */ |
| 25 | #define GPT_L1_INDEX_MASK ULL(0xf) |
| 26 | #define GPT_L1_INDEX_SHIFT ULL(0x0) |
| 27 | |
| 28 | #define GPT_TBL_DESC ULL(0x3) |
| 29 | #define GPT_BLK_DESC ULL(0x1) |
| 30 | |
| 31 | #define GPT_TBL_DESC_ADDR_SHIFT ULL(12) |
| 32 | #define GPT_TBL_DESC_ADDR_MASK (((ULL(1) << \ |
| 33 | (51 - GPT_TBL_DESC_ADDR_SHIFT)) - 1) \ |
| 34 | << GPT_TBL_DESC_ADDR_SHIFT) |
| 35 | |
| 36 | #define GPT_BLOCK_DESC_GPI_VAL_SHIFT ULL(4) |
| 37 | |
| 38 | /* Each descriptor is 8 bytes long. */ |
| 39 | #define GPT_DESC_SIZE ULL(8) |
| 40 | |
| 41 | #define PPS_MAX_VAL PSTCR_EL3_PPS_4PB |
| 42 | #define PPS_NUM_1GB_ENTRIES ULL(1024) |
| 43 | #define PGS_4K_1GB_L1_TABLE_SZ (U(2) << 17) |
| 44 | |
| 45 | /* 2 << LOG2_8K = Bytes in 8K */ |
| 46 | #define LOG2_8K U(13) |
| 47 | |
| 48 | #define GPT_L1_SIZE ULL(0x40000) /* 256K */ |
| 49 | #define SZ_1G (ULL(0x1) << 30) /* 1GB */ |
| 50 | |
| 51 | #define GPT_MIN_PGS_SHIFT U(12) /* 4K */ |
| 52 | |
| 53 | #define L1_GPT_INDEX_MASK U(0x3fffffff) |
| 54 | #define GPT_GRAN_DESC_NUM_GPIS U(4) |
| 55 | |
| 56 | #define PAS_REG_GPI_SHIFT U(0) |
| 57 | #define PAS_REG_GPI_MASK U(0xf) |
| 58 | |
| 59 | /* .attrs field definitions */ |
| 60 | #define PAS_REG_DESC_TYPE_ANY U(0) |
| 61 | #define PAS_REG_DESC_TYPE_BLK U(1) |
| 62 | #define PAS_REG_DESC_TYPE_TBL U(2) |
| 63 | #define PAS_REG_DESC_TYPE_SHIFT U(4) |
| 64 | #define PAS_REG_DESC_TYPE_MASK U(0x3) |
| 65 | #define PAS_REG_DESC_TYPE(_attrs) (((_attrs) \ |
| 66 | >> PAS_REG_DESC_TYPE_SHIFT) \ |
| 67 | & PAS_REG_DESC_TYPE_MASK) |
| 68 | |
| 69 | #define PAS_REG_GPI(_attrs) (((_attrs) \ |
| 70 | >> PAS_REG_GPI_SHIFT) \ |
| 71 | & PAS_REG_GPI_MASK) |
| 72 | |
| 73 | #define SZ_1G_MASK (SZ_1G - U(1)) |
| 74 | #define IS_1GB_ALIGNED(addr) (((addr) & SZ_1G_MASK) == U(0)) |
| 75 | |
| 76 | #endif /* GPT_DEFS */ |