| Ghennadi Procopciuc | 8b81a39 | 2024-01-30 16:19:47 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright 2024 NXP |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <asm_macros.S> |
| 8 | #include <platform_def.h> |
| 9 | |
| 10 | #define S32G_NCORE_CAIU0_BASE_ADDR UL(0x50400000) |
| 11 | #define S32G_NCORE_CAIUTC_OFF U(0x0) |
| 12 | #define S32G_NCORE_CAIUTC_ISOLEN_SHIFT U(1) |
| 13 | |
| 14 | .globl plat_crash_console_flush |
| 15 | .globl plat_crash_console_init |
| 16 | .globl plat_crash_console_putc |
| 17 | .globl plat_is_my_cpu_primary |
| 18 | .globl plat_reset_handler |
| 19 | .globl plat_secondary_cold_boot_setup |
| 20 | .globl platform_mem_init |
| 21 | .globl s32g2_core_pos_by_mpidr |
| 22 | |
| 23 | /* int plat_crash_console_init(void); */ |
| 24 | func plat_crash_console_init |
| 25 | mov_imm x0, UART_BASE |
| 26 | mov_imm x1, UART_CLOCK_HZ |
| 27 | mov_imm x2, UART_BAUDRATE |
| 28 | b console_linflex_core_init |
| 29 | endfunc plat_crash_console_init |
| 30 | |
| 31 | /* int plat_crash_console_putc(int); */ |
| 32 | func plat_crash_console_putc |
| 33 | mov_imm x1, UART_BASE |
| 34 | b console_linflex_core_putc |
| 35 | ret |
| 36 | endfunc plat_crash_console_putc |
| 37 | |
| 38 | /* void plat_crash_console_flush(void); */ |
| 39 | func plat_crash_console_flush |
| 40 | ret |
| 41 | endfunc plat_crash_console_flush |
| 42 | |
| 43 | /** |
| 44 | * unsigned int s32g2_core_pos_by_mpidr(u_register_t mpidr); |
| 45 | * |
| 46 | * In: x0 - MPIDR_EL1 |
| 47 | * Out: x0 |
| 48 | * Clobber list: x0, x1 |
| 49 | */ |
| 50 | func s32g2_core_pos_by_mpidr |
| 51 | and x1, x0, #MPIDR_CPU_MASK |
| 52 | and x0, x0, #MPIDR_CLUSTER_MASK |
| 53 | lsr x0, x0, #MPIDR_AFF1_SHIFT |
| 54 | add x0, x1, x0, lsl #PLATFORM_MPIDR_CPU_MASK_BITS |
| 55 | ret |
| 56 | endfunc s32g2_core_pos_by_mpidr |
| 57 | |
| 58 | /** |
| 59 | * unsigned int plat_my_core_pos(void); |
| 60 | * |
| 61 | * Out: x0 |
| 62 | * Clobber list: x0, x1, x8 |
| 63 | */ |
| 64 | func plat_my_core_pos |
| 65 | mov x8, x30 |
| 66 | mrs x0, mpidr_el1 |
| 67 | bl s32g2_core_pos_by_mpidr |
| 68 | mov x30, x8 |
| 69 | ret |
| 70 | endfunc plat_my_core_pos |
| 71 | |
| 72 | /** |
| 73 | * unsigned int plat_is_my_cpu_primary(void); |
| 74 | * |
| 75 | * Clobber list: x0, x1, x7, x8 |
| 76 | */ |
| 77 | func plat_is_my_cpu_primary |
| 78 | mov x7, x30 |
| 79 | bl plat_my_core_pos |
| 80 | cmp x0, #PLATFORM_PRIMARY_CPU |
| 81 | cset x0, eq |
| 82 | mov x30, x7 |
| 83 | ret |
| 84 | endfunc plat_is_my_cpu_primary |
| 85 | |
| 86 | |
| 87 | /** |
| 88 | * void plat_secondary_cold_boot_setup (void); |
| 89 | */ |
| 90 | func plat_secondary_cold_boot_setup |
| 91 | ret |
| 92 | endfunc plat_secondary_cold_boot_setup |
| 93 | |
| 94 | /** |
| 95 | * void plat_reset_handler(void); |
| 96 | * |
| 97 | * Set the CAIUTC[IsolEn] bit for the primary A53 cluster. |
| 98 | * This is so cache invalidate operations from the early TF-A boot code |
| 99 | * won't cause Ncore to crash. |
| 100 | * |
| 101 | * Clobber list: x0, x1, x2 |
| 102 | */ |
| 103 | func plat_reset_handler |
| 104 | mov x0, #S32G_NCORE_CAIU0_BASE_ADDR |
| 105 | ldr w1, [x0, #S32G_NCORE_CAIUTC_OFF] |
| 106 | movz w2, #1 |
| 107 | lsl w2, w2, #S32G_NCORE_CAIUTC_ISOLEN_SHIFT |
| 108 | orr w1, w1, w2 |
| 109 | str w1, [x0, #S32G_NCORE_CAIUTC_OFF] |
| 110 | ret |
| 111 | endfunc plat_reset_handler |
| 112 | |
| 113 | /* void platform_mem_init(void); */ |
| 114 | func platform_mem_init |
| 115 | mov x10, x30 |
| 116 | mov x0, #BL31_BASE |
| 117 | mov x1, #(BL31_LIMIT & 0xFFFFU) |
| 118 | movk x1, #(BL31_LIMIT >> 16), lsl #16 |
| 119 | sub x1, x1, x0 |
| 120 | bl zeromem |
| 121 | mov x0, #BL33_BASE |
| 122 | mov x1, #(BL33_LIMIT & 0xFFFFU) |
| 123 | movk x1, #(BL33_LIMIT >> 16), lsl #16 |
| 124 | sub x1, x1, x0 |
| 125 | bl zeromem |
| 126 | mov x30, x10 |
| 127 | ret |
| 128 | endfunc platform_mem_init |
| 129 | |