blob: a4fdb3bd3083fa4e0e8c453885a6dbae2e800066 [file] [log] [blame]
Boyan Karatotevc73686a2023-02-15 13:21:50 +00001/*
2 * Copyright (c) 2023, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <arch_features.h>
9#include <arch_helpers.h>
10#include <lib/extensions/pmuv3.h>
11
12/*
13 * Applies to all PMU versions. Name is PMUv3 for compatibility with aarch64 and
14 * to not clash with platforms which reuse the PMU name
15 */
16void pmuv3_disable_el3(void)
17{
18 u_register_t sdcr = read_sdcr();
19
20 /* ---------------------------------------------------------------------
21 * Initialise SDCR, setting all the fields rather than relying on hw.
22 *
23 * SDCR.SCCD: Set to one so that cycle counting by PMCCNTR is prohibited
24 * in Secure state. This bit is RES0 in versions of the architecture
25 * earlier than ARMv8.5
26 *
27 * SDCR.SPME: Set to zero so that event counting is prohibited in Secure
28 * state (and explicitly EL3 with later revisions). If ARMv8.2 Debug is
29 * not implemented this bit does not have any effect on the counters
30 * unless there is support for the implementation defined
31 * authentication interface ExternalSecureNoninvasiveDebugEnabled().
32 * ---------------------------------------------------------------------
33 */
34 sdcr = (sdcr | SDCR_SCCD_BIT) & ~SDCR_SPME_BIT;
35 write_sdcr(sdcr);
36
37 /* ---------------------------------------------------------------------
38 * Initialise PMCR, setting all fields rather than relying
39 * on hw. Some fields are architecturally UNKNOWN on reset.
40 *
41 * PMCR.DP: Set to one to prohibit cycle counting whilst in Secure mode.
42 *
43 * PMCR.X: Set to zero to disable export of events.
44 *
45 * PMCR.C: Set to one to reset PMCCNTR.
46 *
47 * PMCR.P: Set to one to reset each event counter PMEVCNTR<n> to zero.
48 *
49 * PMCR.E: Set to zero to disable cycle and event counters.
50 * ---------------------------------------------------------------------
51 */
52
53 write_pmcr(read_pmcr() | PMCR_DP_BIT | PMCR_C_BIT | PMCR_P_BIT |
54 ~(PMCR_X_BIT | PMCR_E_BIT));
55}