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Manish V Badarkhe813524e2021-07-02 09:10:56 +01001/*
Boyan Karatotev60d330d2023-02-16 15:12:45 +00002 * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
Manish V Badarkhe813524e2021-07-02 09:10:56 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
Jayanth Dodderi Chidanand47c681b2022-05-19 14:08:28 +01008#include <arch_features.h>
Manish V Badarkhe813524e2021-07-02 09:10:56 +01009#include <arch_helpers.h>
10#include <lib/el3_runtime/pubsub.h>
11#include <lib/extensions/trbe.h>
12
13static void tsb_csync(void)
14{
15 /*
16 * The assembler does not yet understand the tsb csync mnemonic
17 * so use the equivalent hint instruction.
18 */
19 __asm__ volatile("hint #18");
20}
21
Boyan Karatotev60d330d2023-02-16 15:12:45 +000022void trbe_init_el3(void)
Manish V Badarkhe813524e2021-07-02 09:10:56 +010023{
Boyan Karatotev60d330d2023-02-16 15:12:45 +000024 u_register_t val;
Manish V Badarkhe813524e2021-07-02 09:10:56 +010025
Andre Przywaraf5360cf2022-11-17 16:42:09 +000026 /*
Boyan Karatotevece8f7d2023-02-13 16:32:47 +000027 * MDCR_EL3.NSTBE = 0b0
28 * Trace Buffer owning Security state is Non-secure state. If FEAT_RME
29 * is not implemented, this field is RES0.
30 *
Andre Przywaraf5360cf2022-11-17 16:42:09 +000031 * MDCR_EL3.NSTB = 0b11
Boyan Karatotevece8f7d2023-02-13 16:32:47 +000032 * Allow access of trace buffer control registers from NS-EL1 and
33 * NS-EL2, tracing is prohibited in Secure and Realm state (if
34 * implemented).
Andre Przywaraf5360cf2022-11-17 16:42:09 +000035 */
36 val = read_mdcr_el3();
37 val |= MDCR_NSTB(MDCR_NSTB_EL1);
Boyan Karatotevece8f7d2023-02-13 16:32:47 +000038 val &= ~(MDCR_NSTBE_BIT);
Andre Przywaraf5360cf2022-11-17 16:42:09 +000039 write_mdcr_el3(val);
Manish V Badarkhe813524e2021-07-02 09:10:56 +010040}
41
Arvind Ram Prakashc7d94652024-07-19 11:39:49 -050042void trbe_disable(void)
43{
44 u_register_t mdcr_el3_val = read_mdcr_el3();
45
46 /*
47 * MDCR_EL3.NSTBE = 0b0
48 * Trace Buffer owning Security state is secure state. If FEAT_RME
49 * is not implemented, this field is RES0.
50 *
51 * MDCR_EL3.NSTB = 0b00
52 * Clear these bits to disable access of trace buffer control registers
53 * from lower ELs in any security state.
54 */
55 mdcr_el3_val &= ~(MDCR_NSTB(MDCR_NSTB_EL1));
56 mdcr_el3_val &= ~(MDCR_NSTBE_BIT);
57 write_mdcr_el3(mdcr_el3_val);
58}
59
Boyan Karatotev60d330d2023-02-16 15:12:45 +000060void trbe_init_el2_unused(void)
61{
62 /*
63 * MDCR_EL2.E2TB: Set to zero so that the trace Buffer
64 * owning exception level is NS-EL1 and, tracing is
65 * prohibited at NS-EL2. These bits are RES0 when
66 * FEAT_TRBE is not implemented.
67 */
68 write_mdcr_el2(read_mdcr_el2() & ~MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1));
69}
70
Manish V Badarkhe813524e2021-07-02 09:10:56 +010071static void *trbe_drain_trace_buffers_hook(const void *arg __unused)
72{
Andre Przywaraf5360cf2022-11-17 16:42:09 +000073 if (is_feat_trbe_supported()) {
Manish V Badarkhe813524e2021-07-02 09:10:56 +010074 /*
75 * Before switching from normal world to secure world
76 * the trace buffers need to be drained out to memory. This is
77 * required to avoid an invalid memory access when TTBR is switched
78 * for entry to S-EL1.
79 */
80 tsb_csync();
81 dsbnsh();
82 }
83
84 return (void *)0;
85}
86
87SUBSCRIBE_TO_EVENT(cm_entering_secure_world, trbe_drain_trace_buffers_hook);