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review.trustedfirmware.org / TF-A / trusted-firmware-a / 0781f7804a6922b3bb40f2b50880a9563e8ccd84 / . / plat / mediatek / mt8196 / include / platform_def.h
blob: abc9d8fd54a6b02f34328da04ade6c0a0b9b46ee [file] [log] [blame]
Gavin Liua65fadf2024-10-21 14:22:19 +0800[diff] [blame]1/*
2 * Copyright (c) 2024, Mediatek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
9
10#include <arch.h>
11#include <plat/common/common_def.h>
12
13#include <arch_def.h>
14
15#define PLAT_PRIMARY_CPU (0x0)
16
17#define MT_GIC_BASE (0x0C400000)
18#define MCUCFG_BASE (0x0C000000)
19#define MCUCFG_REG_SIZE (0x50000)
20#define IO_PHYS (0x10000000)
21
22/* Aggregate of all devices for MMU mapping */
23#define MTK_DEV_RNG1_BASE (IO_PHYS)
24#define MTK_DEV_RNG1_SIZE (0x10000000)
25
26#define TOPCKGEN_BASE (IO_PHYS)
27
28/*******************************************************************************
29 * AUDIO related constants
30 ******************************************************************************/
31#define AUDIO_BASE (IO_PHYS + 0x0a110000)
32
33/*******************************************************************************
Karl Li0781f782024-11-14 15:46:27 +0800[diff] [blame^]34 * APUSYS related constants
35 ******************************************************************************/
36#define APUSYS_BASE (IO_PHYS + 0x09000000)
37#define APUSYS_CE_BASE (IO_PHYS + 0x090B0000)
38
39#define APU_MBOX0 (0x4C200000)
40
41/*******************************************************************************
Gavin Liua65fadf2024-10-21 14:22:19 +0800[diff] [blame]42 * SPM related constants
43 ******************************************************************************/
44#define SPM_BASE (IO_PHYS + 0x0C004000)
45
46/*******************************************************************************
Cathy Xu4cb9f2a2024-02-27 17:07:31 +0800[diff] [blame]47 * GPIO related constants
48 ******************************************************************************/
49#define GPIO_BASE (IO_PHYS + 0x0002D000)
50#define RGU_BASE (IO_PHYS + 0x0C00B000)
51#define DRM_BASE (IO_PHYS + 0x0000D000)
52#define IOCFG_RT_BASE (IO_PHYS + 0x02000000)
53#define IOCFG_RM1_BASE (IO_PHYS + 0x02020000)
54#define IOCFG_RM2_BASE (IO_PHYS + 0x02040000)
55#define IOCFG_RB_BASE (IO_PHYS + 0x02060000)
56#define IOCFG_BM1_BASE (IO_PHYS + 0x02820000)
57#define IOCFG_BM2_BASE (IO_PHYS + 0x02840000)
58#define IOCFG_BM3_BASE (IO_PHYS + 0x02860000)
59#define IOCFG_LT_BASE (IO_PHYS + 0x03000000)
60#define IOCFG_LM1_BASE (IO_PHYS + 0x03020000)
61#define IOCFG_LM2_BASE (IO_PHYS + 0x03040000)
62#define IOCFG_LB1_BASE (IO_PHYS + 0x030f0000)
63#define IOCFG_LB2_BASE (IO_PHYS + 0x03110000)
64#define IOCFG_TM1_BASE (IO_PHYS + 0x03800000)
65#define IOCFG_TM2_BASE (IO_PHYS + 0x03820000)
66#define IOCFG_TM3_BASE (IO_PHYS + 0x03860000)
67
68/*******************************************************************************
Gavin Liua65fadf2024-10-21 14:22:19 +0800[diff] [blame]69 * UART related constants
70 ******************************************************************************/
71#define UART0_BASE (IO_PHYS + 0x06000000)
72#define UART_BAUDRATE (115200)
73
74/*******************************************************************************
75 * Infra IOMMU related constants
76 ******************************************************************************/
77#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
78#define INFRACFG_AO_MEM_BASE (IO_PHYS + 0x00404000)
79#define PERICFG_AO_BASE (IO_PHYS + 0x06630000)
80#define PERICFG_AO_REG_SIZE (0x1000)
81
82/*******************************************************************************
83 * GIC-600 & interrupt handling related constants
84 ******************************************************************************/
85/* Base MTK_platform compatible GIC memory map */
86#define BASE_GICD_BASE (MT_GIC_BASE)
87#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
88#define MTK_GIC_REG_SIZE 0x400000
89
90/*******************************************************************************
91 * MM IOMMU & SMI related constants
92 ******************************************************************************/
93#define SMI_LARB_0_BASE (IO_PHYS + 0x0c022000)
94#define SMI_LARB_1_BASE (IO_PHYS + 0x0c023000)
95#define SMI_LARB_2_BASE (IO_PHYS + 0x0c102000)
96#define SMI_LARB_3_BASE (IO_PHYS + 0x0c103000)
97#define SMI_LARB_4_BASE (IO_PHYS + 0x04013000)
98#define SMI_LARB_5_BASE (IO_PHYS + 0x04f02000)
99#define SMI_LARB_6_BASE (IO_PHYS + 0x04f03000)
100#define SMI_LARB_7_BASE (IO_PHYS + 0x04e04000)
101#define SMI_LARB_9_BASE (IO_PHYS + 0x05001000)
102#define SMI_LARB_10_BASE (IO_PHYS + 0x05120000)
103#define SMI_LARB_11A_BASE (IO_PHYS + 0x05230000)
104#define SMI_LARB_11B_BASE (IO_PHYS + 0x05530000)
105#define SMI_LARB_11C_BASE (IO_PHYS + 0x05630000)
106#define SMI_LARB_12_BASE (IO_PHYS + 0x05340000)
107#define SMI_LARB_13_BASE (IO_PHYS + 0x06001000)
108#define SMI_LARB_14_BASE (IO_PHYS + 0x06002000)
109#define SMI_LARB_15_BASE (IO_PHYS + 0x05140000)
110#define SMI_LARB_16A_BASE (IO_PHYS + 0x06008000)
111#define SMI_LARB_16B_BASE (IO_PHYS + 0x0600a000)
112#define SMI_LARB_17A_BASE (IO_PHYS + 0x06009000)
113#define SMI_LARB_17B_BASE (IO_PHYS + 0x0600b000)
114#define SMI_LARB_19_BASE (IO_PHYS + 0x0a010000)
115#define SMI_LARB_21_BASE (IO_PHYS + 0x0802e000)
116#define SMI_LARB_23_BASE (IO_PHYS + 0x0800d000)
117#define SMI_LARB_27_BASE (IO_PHYS + 0x07201000)
118#define SMI_LARB_28_BASE (IO_PHYS + 0x00000000)
119#define SMI_LARB_REG_RNG_SIZE (0x1000)
120
121/*******************************************************************************
122 * APMIXEDSYS related constants
123 ******************************************************************************/
124#define APMIXEDSYS (IO_PHYS + 0x0000C000)
125
126/*******************************************************************************
127 * VPPSYS related constants
128 ******************************************************************************/
129#define VPPSYS0_BASE (IO_PHYS + 0x04000000)
130#define VPPSYS1_BASE (IO_PHYS + 0x04f00000)
131
132/*******************************************************************************
133 * VDOSYS related constants
134 ******************************************************************************/
135#define VDOSYS0_BASE (IO_PHYS + 0x0C01D000)
136#define VDOSYS1_BASE (IO_PHYS + 0x0C100000)
137
138/*******************************************************************************
Mac Shen3e43d1d2024-12-10 14:15:20 +0800[diff] [blame]139 * DP related constants
140 ******************************************************************************/
141#define EDP_SEC_BASE (IO_PHYS + 0x2EC50000)
142#define DP_SEC_BASE (IO_PHYS + 0x2EC10000)
143#define EDP_SEC_SIZE (0x1000)
144#define DP_SEC_SIZE (0x1000)
145
146/*******************************************************************************
Gavin Liua65fadf2024-10-21 14:22:19 +0800[diff] [blame]147 * EMI MPU related constants
148 *******************************************************************************/
149#define EMI_MPU_BASE (IO_PHYS + 0x00428000)
150#define SUB_EMI_MPU_BASE (IO_PHYS + 0x00528000)
151
152/*******************************************************************************
153 * System counter frequency related constants
154 ******************************************************************************/
155#define SYS_COUNTER_FREQ_IN_HZ (13000000)
156#define SYS_COUNTER_FREQ_IN_MHZ (13)
157
158/*******************************************************************************
159 * Generic platform constants
160 ******************************************************************************/
161#define PLATFORM_STACK_SIZE (0x800)
162#define SOC_CHIP_ID U(0x8196)
163
164/*******************************************************************************
165 * Platform memory map related constants
166 ******************************************************************************/
167#define TZRAM_BASE (0x94600000)
168#define TZRAM_SIZE (0x00200000)
169
170/*******************************************************************************
171 * BL31 specific defines.
172 ******************************************************************************/
173/*
174 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
175 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a
176 * little space for growth.
177 */
178#define BL31_BASE (TZRAM_BASE + 0x1000)
179#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
180
181/*******************************************************************************
182 * Platform specific page table and MMU setup constants
183 ******************************************************************************/
184#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39)
185#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39)
186#define MAX_XLAT_TABLES (128)
187#define MAX_MMAP_REGIONS (512)
188
189/*******************************************************************************
190 * CPU PM definitions
191 *******************************************************************************/
192#define PLAT_CPU_PM_B_BUCK_ISO_ID (6)
193#define PLAT_CPU_PM_ILDO_ID (6)
194#define CPU_IDLE_SRAM_BASE (0x11B000)
195#define CPU_IDLE_SRAM_SIZE (0x1000)
196
197/*******************************************************************************
198 * SYSTIMER related definitions
199 ******************************************************************************/
200#define SYSTIMER_BASE (0x1C400000)
201
202#endif /* PLATFORM_DEF_H */