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Dan Handleyb4315302015-03-19 18:58:55 +00001/*
2 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30#include <arch.h>
31#include <asm_macros.S>
32#include <cpu_macros.S>
33#include <css_def.h>
34
35 .weak plat_secondary_cold_boot_setup
Soby Mathew38dce702015-07-01 16:16:20 +010036 .weak plat_get_my_entrypoint
Dan Handleyb4315302015-03-19 18:58:55 +000037 .weak platform_mem_init
Soby Mathew38dce702015-07-01 16:16:20 +010038 .globl plat_arm_calc_core_pos
39 .weak plat_is_my_cpu_primary
Dan Handleyb4315302015-03-19 18:58:55 +000040
41 /* -----------------------------------------------------
42 * void plat_secondary_cold_boot_setup (void);
43 *
44 * This function performs any platform specific actions
45 * needed for a secondary cpu after a cold reset e.g
46 * mark the cpu's presence, mechanism to place it in a
47 * holding pen etc.
48 * -----------------------------------------------------
49 */
50func plat_secondary_cold_boot_setup
51 /* todo: Implement secondary CPU cold boot setup on CSS platforms */
52cb_panic:
53 b cb_panic
54endfunc plat_secondary_cold_boot_setup
55
Sandrine Bailleux804040d2015-07-10 16:49:31 +010056 /* ---------------------------------------------------------------------
Soby Mathew38dce702015-07-01 16:16:20 +010057 * unsigned long plat_get_my_entrypoint (void);
Dan Handleyb4315302015-03-19 18:58:55 +000058 *
Sandrine Bailleux804040d2015-07-10 16:49:31 +010059 * Main job of this routine is to distinguish between a cold and a warm
60 * boot. On CSS platforms, this distinction is based on the contents of
61 * the Trusted Mailbox. It is initialised to zero by the SCP before the
62 * AP cores are released from reset. Therefore, a zero mailbox means
63 * it's a cold reset.
Dan Handleyb4315302015-03-19 18:58:55 +000064 *
Sandrine Bailleux804040d2015-07-10 16:49:31 +010065 * This functions returns the contents of the mailbox, i.e.:
66 * - 0 for a cold boot;
67 * - the warm boot entrypoint for a warm boot.
68 * ---------------------------------------------------------------------
Dan Handleyb4315302015-03-19 18:58:55 +000069 */
Soby Mathew38dce702015-07-01 16:16:20 +010070func plat_get_my_entrypoint
Sandrine Bailleux804040d2015-07-10 16:49:31 +010071 mov_imm x0, TRUSTED_MAILBOX_BASE
72 ldr x0, [x0]
73 ret
Soby Mathew38dce702015-07-01 16:16:20 +010074endfunc plat_get_my_entrypoint
Dan Handleyb4315302015-03-19 18:58:55 +000075
Soby Mathew38dce702015-07-01 16:16:20 +010076 /* -----------------------------------------------------------
77 * unsigned int plat_arm_calc_core_pos(uint64_t mpidr)
78 * Function to calculate the core position by
79 * swapping the cluster order. This is necessary in order to
80 * match the format of the boot information passed by the SCP
81 * and read in platform_is_primary_cpu below.
82 * -----------------------------------------------------------
Dan Handleyb4315302015-03-19 18:58:55 +000083 */
Soby Mathew38dce702015-07-01 16:16:20 +010084func plat_arm_calc_core_pos
Dan Handleyb4315302015-03-19 18:58:55 +000085 and x1, x0, #MPIDR_CPU_MASK
86 and x0, x0, #MPIDR_CLUSTER_MASK
87 eor x0, x0, #(1 << MPIDR_AFFINITY_BITS) // swap cluster order
88 add x0, x1, x0, LSR #6
89 ret
Soby Mathew38dce702015-07-01 16:16:20 +010090endfunc plat_arm_calc_core_pos
Dan Handleyb4315302015-03-19 18:58:55 +000091
92 /* -----------------------------------------------------
93 * void platform_mem_init(void);
94 *
95 * We don't need to carry out any memory initialization
96 * on CSS platforms. The Secure RAM is accessible straight away.
97 * -----------------------------------------------------
98 */
99func platform_mem_init
100 ret
101endfunc platform_mem_init
102
103 /* -----------------------------------------------------
Soby Mathew38dce702015-07-01 16:16:20 +0100104 * unsigned int plat_is_my_cpu_primary (void);
Dan Handleyb4315302015-03-19 18:58:55 +0000105 *
Soby Mathew38dce702015-07-01 16:16:20 +0100106 * Find out whether the current cpu is the primary
Dan Handleyb4315302015-03-19 18:58:55 +0000107 * cpu (applicable ony after a cold boot)
108 * -----------------------------------------------------
109 */
Soby Mathew38dce702015-07-01 16:16:20 +0100110func plat_is_my_cpu_primary
Dan Handleyb4315302015-03-19 18:58:55 +0000111 mov x9, x30
Soby Mathew38dce702015-07-01 16:16:20 +0100112 bl plat_my_core_pos
Dan Handleyb4315302015-03-19 18:58:55 +0000113 ldr x1, =SCP_BOOT_CFG_ADDR
114 ldr x1, [x1]
Soby Mathew19af6fc2015-05-26 16:58:54 +0100115 ubfx x1, x1, #PRIMARY_CPU_SHIFT, #PRIMARY_CPU_BIT_WIDTH
Dan Handleyb4315302015-03-19 18:58:55 +0000116 cmp x0, x1
117 cset x0, eq
118 ret x9
Soby Mathew38dce702015-07-01 16:16:20 +0100119endfunc plat_is_my_cpu_primary