| Varun Wadekar | 68c7de6 | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 1 | /* |
| Varun Wadekar | 5e2fe3a | 2019-01-11 14:48:41 -0800 | [diff] [blame] | 2 | * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. |
| Pritesh Raithatha | a391d49 | 2018-08-03 15:48:15 +0530 | [diff] [blame] | 3 | * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. |
| Varun Wadekar | 68c7de6 | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 4 | * |
| dp-arm | 82cb2c1 | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 5 | * SPDX-License-Identifier: BSD-3-Clause |
| Varun Wadekar | 68c7de6 | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 6 | */ |
| 7 | |||||
| 8 | #include <arch.h> | ||||
| 9 | #include <asm_macros.S> | ||||
| Varun Wadekar | 5e2fe3a | 2019-01-11 14:48:41 -0800 | [diff] [blame] | 10 | #include <common/bl_common.h> |
| Varun Wadekar | 68c7de6 | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 11 | #include <memctrl_v2.h> |
| Antonio Nino Diaz | 09d40e0 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 12 | #include <plat/common/common_def.h> |
| Varun Wadekar | 68c7de6 | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 13 | #include <tegra_def.h> |
| 14 | |||||
| Pritesh Raithatha | a391d49 | 2018-08-03 15:48:15 +0530 | [diff] [blame] | 15 | #define TEGRA186_MC_CTX_SIZE 0x93 |
| Varun Wadekar | 68c7de6 | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 16 | |
| Varun Wadekar | 2139c9c | 2018-11-09 09:08:16 -0800 | [diff] [blame] | 17 | .globl tegra186_get_mc_ctx_size |
| Varun Wadekar | 68c7de6 | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 18 | |
| 19 | /* | ||||
| Varun Wadekar | 2139c9c | 2018-11-09 09:08:16 -0800 | [diff] [blame] | 20 | * Tegra186 reset data (offset 0x0 - 0x420) |
| Varun Wadekar | 68c7de6 | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 21 | * |
| Varun Wadekar | 2139c9c | 2018-11-09 09:08:16 -0800 | [diff] [blame] | 22 | * 0x000: MC context start |
| 23 | * 0x420: MC context end | ||||
| Varun Wadekar | 68c7de6 | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 24 | */ |
| 25 | |||||
| 26 | .align 4 | ||||
| Pritesh Raithatha | a391d49 | 2018-08-03 15:48:15 +0530 | [diff] [blame] | 27 | __tegra186_mc_context: |
| 28 | .rept TEGRA186_MC_CTX_SIZE | ||||
| Varun Wadekar | 68c7de6 | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 29 | .quad 0 |
| 30 | .endr | ||||
| Varun Wadekar | 68c7de6 | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 31 | |
| 32 | .align 4 | ||||
| Varun Wadekar | 2139c9c | 2018-11-09 09:08:16 -0800 | [diff] [blame] | 33 | __tegra186_mc_context_end: |
| Varun Wadekar | 889c07c | 2017-11-08 14:45:08 -0800 | [diff] [blame] | 34 | |
| Pritesh Raithatha | a391d49 | 2018-08-03 15:48:15 +0530 | [diff] [blame] | 35 | /* return the size of the MC context */ |
| Varun Wadekar | 2139c9c | 2018-11-09 09:08:16 -0800 | [diff] [blame] | 36 | func tegra186_get_mc_ctx_size |
| 37 | adr x0, __tegra186_mc_context_end | ||||
| 38 | adr x1, __tegra186_mc_context | ||||
| Varun Wadekar | 889c07c | 2017-11-08 14:45:08 -0800 | [diff] [blame] | 39 | sub x0, x0, x1 |
| 40 | ret | ||||
| Varun Wadekar | 2139c9c | 2018-11-09 09:08:16 -0800 | [diff] [blame] | 41 | endfunc tegra186_get_mc_ctx_size |