blob: c86fdba058a988c20464195c7077467b5f02f708 [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handley97043ac2014-04-09 13:14:54 +010031#include <arch.h>
Andrew Thoelke0a30cf52014-03-18 13:46:55 +000032#include <asm_macros.S>
Achin Gupta4f6ad662013-10-25 09:08:21 +010033
Achin Gupta4f6ad662013-10-25 09:08:21 +010034 .globl read_vbar_el1
35 .globl read_vbar_el2
36 .globl read_vbar_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +010037 .globl write_vbar_el1
38 .globl write_vbar_el2
39 .globl write_vbar_el3
40
Achin Gupta4f6ad662013-10-25 09:08:21 +010041 .globl read_sctlr_el1
42 .globl read_sctlr_el2
43 .globl read_sctlr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +010044 .globl write_sctlr_el1
45 .globl write_sctlr_el2
46 .globl write_sctlr_el3
47
Achin Gupta4f6ad662013-10-25 09:08:21 +010048 .globl read_actlr_el1
49 .globl read_actlr_el2
50 .globl read_actlr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +010051 .globl write_actlr_el1
52 .globl write_actlr_el2
53 .globl write_actlr_el3
54
Achin Gupta4f6ad662013-10-25 09:08:21 +010055 .globl read_esr_el1
56 .globl read_esr_el2
57 .globl read_esr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +010058 .globl write_esr_el1
59 .globl write_esr_el2
60 .globl write_esr_el3
61
Achin Gupta4f6ad662013-10-25 09:08:21 +010062 .globl read_afsr0_el1
63 .globl read_afsr0_el2
64 .globl read_afsr0_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +010065 .globl write_afsr0_el1
66 .globl write_afsr0_el2
67 .globl write_afsr0_el3
68
Achin Gupta4f6ad662013-10-25 09:08:21 +010069 .globl read_afsr1_el1
70 .globl read_afsr1_el2
71 .globl read_afsr1_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +010072 .globl write_afsr1_el1
73 .globl write_afsr1_el2
74 .globl write_afsr1_el3
75
Achin Gupta4f6ad662013-10-25 09:08:21 +010076 .globl read_far_el1
77 .globl read_far_el2
78 .globl read_far_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +010079 .globl write_far_el1
80 .globl write_far_el2
81 .globl write_far_el3
82
Achin Gupta4f6ad662013-10-25 09:08:21 +010083 .globl read_mair_el1
84 .globl read_mair_el2
85 .globl read_mair_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +010086 .globl write_mair_el1
87 .globl write_mair_el2
88 .globl write_mair_el3
89
Achin Gupta4f6ad662013-10-25 09:08:21 +010090 .globl read_amair_el1
91 .globl read_amair_el2
92 .globl read_amair_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +010093 .globl write_amair_el1
94 .globl write_amair_el2
95 .globl write_amair_el3
96
Achin Gupta4f6ad662013-10-25 09:08:21 +010097 .globl read_rvbar_el1
98 .globl read_rvbar_el2
99 .globl read_rvbar_el3
100
Achin Gupta4f6ad662013-10-25 09:08:21 +0100101 .globl read_rmr_el1
102 .globl read_rmr_el2
103 .globl read_rmr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100104 .globl write_rmr_el1
105 .globl write_rmr_el2
106 .globl write_rmr_el3
107
Achin Gupta4f6ad662013-10-25 09:08:21 +0100108 .globl read_tcr_el1
109 .globl read_tcr_el2
110 .globl read_tcr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100111 .globl write_tcr_el1
112 .globl write_tcr_el2
113 .globl write_tcr_el3
114
Achin Gupta4f6ad662013-10-25 09:08:21 +0100115 .globl read_cptr_el2
116 .globl read_cptr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100117 .globl write_cptr_el2
118 .globl write_cptr_el3
119
Achin Gupta4f6ad662013-10-25 09:08:21 +0100120 .globl read_ttbr0_el1
121 .globl read_ttbr0_el2
122 .globl read_ttbr0_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100123 .globl write_ttbr0_el1
124 .globl write_ttbr0_el2
125 .globl write_ttbr0_el3
126
Achin Gupta4f6ad662013-10-25 09:08:21 +0100127 .globl read_ttbr1_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100128 .globl write_ttbr1_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100129
130 .globl read_cpacr
131 .globl write_cpacr
132
133 .globl read_cntfrq
134 .globl write_cntfrq
135
136 .globl read_cpuectlr
137 .globl write_cpuectlr
138
139 .globl read_cnthctl_el2
140 .globl write_cnthctl_el2
141
142 .globl read_cntfrq_el0
143 .globl write_cntfrq_el0
144
145 .globl read_scr
146 .globl write_scr
147
148 .globl read_hcr
149 .globl write_hcr
150
151 .globl read_midr
152 .globl read_mpidr
153
154 .globl read_current_el
155 .globl read_id_pfr1_el1
156 .globl read_id_aa64pfr0_el1
157
Soby Mathewa43d4312014-04-07 15:28:55 +0100158 .globl write_tpidr_el3
159 .globl read_tpidr_el3
160
Achin Gupta4f6ad662013-10-25 09:08:21 +0100161#if SUPPORT_VFP
162 .globl enable_vfp
Achin Gupta4f6ad662013-10-25 09:08:21 +0100163#endif
164
165
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000166func read_current_el
Achin Gupta4f6ad662013-10-25 09:08:21 +0100167 mrs x0, CurrentEl
168 ret
169
170
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000171func read_id_pfr1_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100172 mrs x0, id_pfr1_el1
173 ret
174
175
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000176func read_id_aa64pfr0_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100177 mrs x0, id_aa64pfr0_el1
178 ret
179
180
181 /* -----------------------------------------------------
182 * VBAR accessors
183 * -----------------------------------------------------
184 */
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000185func read_vbar_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100186 mrs x0, vbar_el1
187 ret
188
189
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000190func read_vbar_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100191 mrs x0, vbar_el2
192 ret
193
194
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000195func read_vbar_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100196 mrs x0, vbar_el3
197 ret
198
199
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000200func write_vbar_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100201 msr vbar_el1, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100202 ret
203
204
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000205func write_vbar_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100206 msr vbar_el2, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100207 ret
208
209
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000210func write_vbar_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100211 msr vbar_el3, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100212 ret
213
214
215 /* -----------------------------------------------------
216 * AFSR0 accessors
217 * -----------------------------------------------------
218 */
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000219func read_afsr0_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100220 mrs x0, afsr0_el1
221 ret
222
223
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000224func read_afsr0_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100225 mrs x0, afsr0_el2
226 ret
227
228
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000229func read_afsr0_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100230 mrs x0, afsr0_el3
231 ret
232
233
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000234func write_afsr0_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100235 msr afsr0_el1, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100236 ret
237
238
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000239func write_afsr0_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100240 msr afsr0_el2, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100241 ret
242
243
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000244func write_afsr0_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100245 msr afsr0_el3, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100246 ret
247
248
249 /* -----------------------------------------------------
250 * FAR accessors
251 * -----------------------------------------------------
252 */
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000253func read_far_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100254 mrs x0, far_el1
255 ret
256
257
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000258func read_far_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100259 mrs x0, far_el2
260 ret
261
262
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000263func read_far_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100264 mrs x0, far_el3
265 ret
266
267
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000268func write_far_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100269 msr far_el1, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100270 ret
271
272
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000273func write_far_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100274 msr far_el2, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100275 ret
276
277
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000278func write_far_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100279 msr far_el3, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100280 ret
281
282
283 /* -----------------------------------------------------
284 * MAIR accessors
285 * -----------------------------------------------------
286 */
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000287func read_mair_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100288 mrs x0, mair_el1
289 ret
290
291
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000292func read_mair_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100293 mrs x0, mair_el2
294 ret
295
296
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000297func read_mair_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100298 mrs x0, mair_el3
299 ret
300
301
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000302func write_mair_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100303 msr mair_el1, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100304 ret
305
306
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000307func write_mair_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100308 msr mair_el2, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100309 ret
310
311
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000312func write_mair_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100313 msr mair_el3, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100314 ret
315
316
317 /* -----------------------------------------------------
318 * AMAIR accessors
319 * -----------------------------------------------------
320 */
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000321func read_amair_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100322 mrs x0, amair_el1
323 ret
324
325
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000326func read_amair_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100327 mrs x0, amair_el2
328 ret
329
330
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000331func read_amair_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100332 mrs x0, amair_el3
333 ret
334
335
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000336func write_amair_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100337 msr amair_el1, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100338 ret
339
340
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000341func write_amair_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100342 msr amair_el2, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100343 ret
344
345
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000346func write_amair_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100347 msr amair_el3, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100348 ret
349
350
351 /* -----------------------------------------------------
352 * RVBAR accessors
353 * -----------------------------------------------------
354 */
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000355func read_rvbar_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100356 mrs x0, rvbar_el1
357 ret
358
359
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000360func read_rvbar_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100361 mrs x0, rvbar_el2
362 ret
363
364
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000365func read_rvbar_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100366 mrs x0, rvbar_el3
367 ret
368
369
370 /* -----------------------------------------------------
371 * RMR accessors
372 * -----------------------------------------------------
373 */
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000374func read_rmr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100375 mrs x0, rmr_el1
376 ret
377
378
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000379func read_rmr_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100380 mrs x0, rmr_el2
381 ret
382
383
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000384func read_rmr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100385 mrs x0, rmr_el3
386 ret
387
388
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000389func write_rmr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100390 msr rmr_el1, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100391 ret
392
393
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000394func write_rmr_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100395 msr rmr_el2, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100396 ret
397
398
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000399func write_rmr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100400 msr rmr_el3, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100401 ret
402
403
Achin Gupta4f6ad662013-10-25 09:08:21 +0100404 /* -----------------------------------------------------
405 * AFSR1 accessors
406 * -----------------------------------------------------
407 */
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000408func read_afsr1_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100409 mrs x0, afsr1_el1
410 ret
411
412
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000413func read_afsr1_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100414 mrs x0, afsr1_el2
415 ret
416
417
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000418func read_afsr1_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100419 mrs x0, afsr1_el3
420 ret
421
422
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000423func write_afsr1_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100424 msr afsr1_el1, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100425 ret
426
427
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000428func write_afsr1_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100429 msr afsr1_el2, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100430 ret
431
432
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000433func write_afsr1_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100434 msr afsr1_el3, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100435 ret
436
437
438 /* -----------------------------------------------------
439 * SCTLR accessors
440 * -----------------------------------------------------
441 */
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000442func read_sctlr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100443 mrs x0, sctlr_el1
444 ret
445
446
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000447func read_sctlr_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100448 mrs x0, sctlr_el2
449 ret
450
451
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000452func read_sctlr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100453 mrs x0, sctlr_el3
454 ret
455
456
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000457func write_sctlr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100458 msr sctlr_el1, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100459 ret
460
461
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000462func write_sctlr_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100463 msr sctlr_el2, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100464 ret
465
466
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000467func write_sctlr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100468 msr sctlr_el3, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100469 ret
470
471
472 /* -----------------------------------------------------
473 * ACTLR accessors
474 * -----------------------------------------------------
475 */
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000476func read_actlr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100477 mrs x0, actlr_el1
478 ret
479
480
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000481func read_actlr_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100482 mrs x0, actlr_el2
483 ret
484
485
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000486func read_actlr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100487 mrs x0, actlr_el3
488 ret
489
490
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000491func write_actlr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100492 msr actlr_el1, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100493 ret
494
495
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000496func write_actlr_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100497 msr actlr_el2, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100498 ret
499
500
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000501func write_actlr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100502 msr actlr_el3, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100503 ret
504
505
506 /* -----------------------------------------------------
507 * ESR accessors
508 * -----------------------------------------------------
509 */
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000510func read_esr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100511 mrs x0, esr_el1
512 ret
513
514
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000515func read_esr_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100516 mrs x0, esr_el2
517 ret
518
519
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000520func read_esr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100521 mrs x0, esr_el3
522 ret
523
524
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000525func write_esr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100526 msr esr_el1, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100527 ret
528
529
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000530func write_esr_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100531 msr esr_el2, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100532 ret
533
534
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000535func write_esr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100536 msr esr_el3, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100537 ret
538
539
540 /* -----------------------------------------------------
541 * TCR accessors
542 * -----------------------------------------------------
543 */
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000544func read_tcr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100545 mrs x0, tcr_el1
546 ret
547
548
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000549func read_tcr_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100550 mrs x0, tcr_el2
551 ret
552
553
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000554func read_tcr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100555 mrs x0, tcr_el3
556 ret
557
558
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000559func write_tcr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100560 msr tcr_el1, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100561 ret
562
563
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000564func write_tcr_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100565 msr tcr_el2, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100566 ret
567
568
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000569func write_tcr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100570 msr tcr_el3, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100571 ret
572
573
574 /* -----------------------------------------------------
575 * CPTR accessors
576 * -----------------------------------------------------
577 */
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000578func read_cptr_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100579 mrs x0, cptr_el2
580 ret
581
582
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000583func read_cptr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100584 mrs x0, cptr_el3
585 ret
586
587
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000588func write_cptr_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100589 msr cptr_el2, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100590 ret
591
592
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000593func write_cptr_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100594 msr cptr_el3, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100595 ret
596
597
598 /* -----------------------------------------------------
599 * TTBR0 accessors
600 * -----------------------------------------------------
601 */
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000602func read_ttbr0_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100603 mrs x0, ttbr0_el1
604 ret
605
606
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000607func read_ttbr0_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100608 mrs x0, ttbr0_el2
609 ret
610
611
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000612func read_ttbr0_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100613 mrs x0, ttbr0_el3
614 ret
615
616
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000617func write_ttbr0_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100618 msr ttbr0_el1, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100619 ret
620
621
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000622func write_ttbr0_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100623 msr ttbr0_el2, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100624 ret
625
626
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000627func write_ttbr0_el3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100628 msr ttbr0_el3, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100629 ret
630
631
632 /* -----------------------------------------------------
633 * TTBR1 accessors
634 * -----------------------------------------------------
635 */
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000636func read_ttbr1_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100637 mrs x0, ttbr1_el1
638 ret
639
640
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000641func write_ttbr1_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100642 msr ttbr1_el1, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100643 ret
644
645
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000646func read_hcr
Achin Gupta4f6ad662013-10-25 09:08:21 +0100647 mrs x0, hcr_el2
648 ret
649
650
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000651func write_hcr
Achin Gupta4f6ad662013-10-25 09:08:21 +0100652 msr hcr_el2, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100653 ret
654
655
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000656func read_cpacr
Achin Gupta4f6ad662013-10-25 09:08:21 +0100657 mrs x0, cpacr_el1
658 ret
659
660
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000661func write_cpacr
Achin Gupta4f6ad662013-10-25 09:08:21 +0100662 msr cpacr_el1, x0
663 ret
664
665
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000666func read_cntfrq_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100667 mrs x0, cntfrq_el0
668 ret
669
670
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000671func write_cntfrq_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100672 msr cntfrq_el0, x0
673 ret
674
675
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000676func read_cpuectlr
Achin Gupta4f6ad662013-10-25 09:08:21 +0100677 mrs x0, CPUECTLR_EL1
678 ret
679
680
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000681func write_cpuectlr
Achin Gupta4f6ad662013-10-25 09:08:21 +0100682 msr CPUECTLR_EL1, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100683 ret
684
685
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000686func read_cnthctl_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100687 mrs x0, cnthctl_el2
688 ret
689
690
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000691func write_cnthctl_el2
Achin Gupta4f6ad662013-10-25 09:08:21 +0100692 msr cnthctl_el2, x0
693 ret
694
695
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000696func read_cntfrq
Achin Gupta4f6ad662013-10-25 09:08:21 +0100697 mrs x0, cntfrq_el0
698 ret
699
700
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000701func write_cntfrq
Achin Gupta4f6ad662013-10-25 09:08:21 +0100702 msr cntfrq_el0, x0
703 ret
704
705
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000706func write_scr
Achin Gupta4f6ad662013-10-25 09:08:21 +0100707 msr scr_el3, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100708 ret
709
710
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000711func read_scr
Achin Gupta4f6ad662013-10-25 09:08:21 +0100712 mrs x0, scr_el3
713 ret
714
715
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000716func read_midr
Achin Gupta4f6ad662013-10-25 09:08:21 +0100717 mrs x0, midr_el1
718 ret
719
720
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000721func read_mpidr
Achin Gupta4f6ad662013-10-25 09:08:21 +0100722 mrs x0, mpidr_el1
723 ret
724
Soby Mathewa43d4312014-04-07 15:28:55 +0100725func write_tpidr_el3
726 msr tpidr_el3, x0
727 ret
728
729func read_tpidr_el3
730 mrs x0, tpidr_el3
731 ret
Achin Gupta4f6ad662013-10-25 09:08:21 +0100732
733#if SUPPORT_VFP
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000734func enable_vfp
Achin Gupta4f6ad662013-10-25 09:08:21 +0100735 mrs x0, cpacr_el1
736 orr x0, x0, #CPACR_VFP_BITS
737 msr cpacr_el1, x0
738 mrs x0, cptr_el3
739 mov x1, #AARCH64_CPTR_TFP
740 bic x0, x0, x1
741 msr cptr_el3, x0
Andrew Thoelke8cec5982014-04-28 12:28:39 +0100742 isb
Achin Gupta4f6ad662013-10-25 09:08:21 +0100743 ret
744
Achin Gupta4f6ad662013-10-25 09:08:21 +0100745#endif