Add files to eliminate HAL dependency, build/compile pass
Signed-off-by: Bohdan Kovalchuk <bohd@cypress.com>
Signed-off-by: Roman Okhrimenko <roman.okhrimenko@cypress.com>
diff --git a/boot/cypress/platforms/cycfg_peripherals.c b/boot/cypress/platforms/cycfg_peripherals.c
new file mode 100644
index 0000000..1c55938
--- /dev/null
+++ b/boot/cypress/platforms/cycfg_peripherals.c
@@ -0,0 +1,73 @@
+/*******************************************************************************
+* File Name: cycfg_peripherals.c
+*
+* Description:
+* Peripheral Hardware Block configuration
+* This file was automatically generated and should not be modified.
+* Device Configurator: 2.0.0.1483
+* Device Support Library (../../../psoc6pdl): 1.3.1.1499
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_peripherals.h"
+
+const cy_stc_scb_uart_config_t CYBSP_UART_config =
+{
+ .uartMode = CY_SCB_UART_STANDARD,
+ .enableMutliProcessorMode = false,
+ .smartCardRetryOnNack = false,
+ .irdaInvertRx = false,
+ .irdaEnableLowPowerReceiver = false,
+ .oversample = 8,
+ .enableMsbFirst = false,
+ .dataWidth = 8UL,
+ .parity = CY_SCB_UART_PARITY_NONE,
+ .stopBits = CY_SCB_UART_STOP_BITS_1,
+ .enableInputFilter = false,
+ .breakWidth = 11UL,
+ .dropOnFrameError = false,
+ .dropOnParityError = false,
+ .receiverAddress = 0x0UL,
+ .receiverAddressMask = 0x0UL,
+ .acceptAddrInFifo = false,
+ .enableCts = false,
+ .ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
+ .rtsRxFifoLevel = 0UL,
+ .rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
+ .rxFifoTriggerLevel = 0UL,
+ .rxFifoIntEnableMask = 0UL,
+ .txFifoTriggerLevel = 63UL,
+ .txFifoIntEnableMask = 0UL,
+};
+#if defined (CY_USING_HAL)
+ const cyhal_resource_inst_t CYBSP_UART_obj =
+ {
+ .type = CYHAL_RSC_SCB,
+ .block_num = 5U,
+ .channel_num = 0U,
+ };
+#endif //defined (CY_USING_HAL)
+
+
+void init_cycfg_peripherals(void)
+{
+ Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_16_BIT, 0U);
+#if defined (CY_USING_HAL)
+ cyhal_hwmgr_reserve(&CYBSP_UART_obj);
+#endif //defined (CY_USING_HAL)
+}