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review.trustedfirmware.org / TF-A / tf-a-tests / 2198e9a1fb8c48c68dc9aa5180ef6ceaca135c29 / . / tftf / framework / aarch32 / entrypoint.S
blob: eaa078831154e0b1eb7d9c6d293dd111dfcfc5dd [file] [log] [blame]
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]1/*
Alexei Fedorov2198e9a2019-12-12 14:14:55 +0000[diff] [blame^]2 * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <tftf.h>
10
11 .globl tftf_entrypoint
12 .globl tftf_hotplug_entry
13
14/* ----------------------------------------------------------------------------
15 * Cold boot entry point for the primary CPU.
16 * ----------------------------------------------------------------------------
17 */
18func tftf_entrypoint
Sandrine Bailleux39caa2c2018-12-18 10:53:34 +0100[diff] [blame]19 bl arch_init
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]20
21 /* --------------------------------------------------------------------
Alexei Fedorov2198e9a2019-12-12 14:14:55 +0000[diff] [blame^]22 * Invalidate the RW memory used by TFTF image.
23 * This is done to safeguard against possible corruption of this
24 * memory by dirty cache lines in a system cache as a result of use
25 * by an earlier boot loader stage.
26 * --------------------------------------------------------------------
27 */
28 ldr r0, =__DATA_START__
29 ldr r1, =__DATA_END__
30 sub r1, r1, r0
31 bl inv_dcache_range
32
33 /* --------------------------------------------------------------------
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]34 * This code is expected to be executed only by the primary CPU.
35 * Save the mpid for the first core that executes and if a secondary
36 * CPU has lost its way make it spin forever.
37 * --------------------------------------------------------------------
38 */
39 bl save_primary_mpid
40
41 /* --------------------------------------------------------------------
42 * Zero out NOBITS sections. There are 2 of them:
43 * - the .bss section;
44 * - the coherent memory section.
45 * --------------------------------------------------------------------
46 */
47 ldr r0, =__BSS_START__
48 ldr r1, =__BSS_SIZE__
49 bl zeromem
50
51 ldr r0, =__COHERENT_RAM_START__
52 ldr r1, =__COHERENT_RAM_UNALIGNED_SIZE__
53 bl zeromem
54
55 /* --------------------------------------------------------------------
56 * Give ourselves a small coherent stack to ease the pain of
57 * initializing the MMU
58 * --------------------------------------------------------------------
59 */
60 ldcopr r0, MPIDR
61 bl platform_set_coherent_stack
62
63 bl tftf_early_platform_setup
64 bl tftf_plat_arch_setup
65
66 /* --------------------------------------------------------------------
67 * Give ourselves a stack allocated in Normal -IS-WBWA memory
68 * --------------------------------------------------------------------
69 */
70 ldcopr r0, MPIDR
71 bl platform_set_stack
72
73 /* --------------------------------------------------------------------
74 * tftf_cold_boot_main() will perform the remaining architectural and
75 * platform setup, initialise the test framework's state, then run the
76 * tests.
77 * --------------------------------------------------------------------
78 */
79 b tftf_cold_boot_main
80endfunc tftf_entrypoint
81
82/* ----------------------------------------------------------------------------
83 * Entry point for a CPU that has just been powered up.
84 * In : r0 - context_id
85 * ----------------------------------------------------------------------------
86 */
87func tftf_hotplug_entry
88
89 /* --------------------------------------------------------------------
90 * Preserve the context_id in a callee-saved register
91 * --------------------------------------------------------------------
92 */
93 mov r4, r0
94
Sandrine Bailleux39caa2c2018-12-18 10:53:34 +0100[diff] [blame]95 bl arch_init
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]96
97 /* --------------------------------------------------------------------
98 * Give ourselves a small coherent stack to ease the pain of
99 * initializing the MMU
100 * --------------------------------------------------------------------
101 */
102 ldcopr r0, MPIDR
103 bl platform_set_coherent_stack
104
105 /* --------------------------------------------------------------------
106 * Enable the MMU
107 * --------------------------------------------------------------------
108 */
109 bl tftf_plat_enable_mmu
110
111 /* --------------------------------------------------------------------
112 * Give ourselves a stack in normal memory.
113 * --------------------------------------------------------------------
114 */
115 ldcopr r0, MPIDR
116 bl platform_set_stack
117
118 /* --------------------------------------------------------------------
119 * Save the context_id for later retrieval by tests
120 * --------------------------------------------------------------------
121 */
122 ldcopr r0, MPIDR
123 ldr r1, =MPID_MASK
124 and r0, r0, r1
125 bl platform_get_core_pos
126
127 mov r1, r4
128
129 bl tftf_set_cpu_on_ctx_id
130
131 /* --------------------------------------------------------------------
132 * Jump to warm boot main function
133 * --------------------------------------------------------------------
134 */
135 b tftf_warm_boot_main
136endfunc tftf_hotplug_entry
137
138/* ----------------------------------------------------------------------------
Sandrine Bailleux39caa2c2018-12-18 10:53:34 +0100[diff] [blame]139 * Initialize architectural state.
140 * ----------------------------------------------------------------------------
141 */
142func arch_init
143 /* Set the exception vectors. */
144 ldr r0, =tftf_vector
145 stcopr r0, HVBAR
146
147 /* Enable the instruction cache. */
148 ldr r0, =(HSCTLR_RES1 | HSCTLR_I_BIT)
149 stcopr r0, HSCTLR
150
151 isb
152 bx lr
153endfunc arch_init
154
155/* ----------------------------------------------------------------------------
Sandrine Bailleux3cd87d72018-10-09 11:12:55 +0200[diff] [blame]156 * Saves the mpid of the primary core and if the primary core
157 * is already saved then it loops infinitely.
158 * ----------------------------------------------------------------------------
159 */
160func save_primary_mpid
161 ldr r1, =tftf_primary_core
162 ldr r0, [r1]
163 mov r2, #INVALID_MPID
164 cmp r0, r2
165 bne panic
166 ldr r2, =MPID_MASK
167 ldcopr r0, MPIDR
168 and r0, r0, r2
169 str r0, [r1]
170 bx lr
171panic:
172 /* Primary core MPID already saved */
173 b panic
174endfunc save_primary_mpid