TrustedFirmware Git Browser
Code Review Sign In
review.trustedfirmware.org / TF-A / trusted-firmware-a / 83f836c96238c0d0765d94cc1f8ed1c179d1878c / . / plat / mediatek / mt8196 / include / platform_def.h
blob: 50a8a3335e5649c1c2a63bedd3f8de14680253c4 [file] [log] [blame]
Gavin Liua65fadf2024-10-21 14:22:19 +0800[diff] [blame]1/*
2 * Copyright (c) 2024, Mediatek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
9
10#include <arch.h>
11#include <plat/common/common_def.h>
12
13#include <arch_def.h>
14
15#define PLAT_PRIMARY_CPU (0x0)
16
17#define MT_GIC_BASE (0x0C400000)
18#define MCUCFG_BASE (0x0C000000)
19#define MCUCFG_REG_SIZE (0x50000)
20#define IO_PHYS (0x10000000)
21
22/* Aggregate of all devices for MMU mapping */
23#define MTK_DEV_RNG1_BASE (IO_PHYS)
24#define MTK_DEV_RNG1_SIZE (0x10000000)
25
26#define TOPCKGEN_BASE (IO_PHYS)
27
28/*******************************************************************************
29 * AUDIO related constants
30 ******************************************************************************/
31#define AUDIO_BASE (IO_PHYS + 0x0a110000)
32
33/*******************************************************************************
Karl Li0781f782024-11-14 15:46:27 +0800[diff] [blame]34 * APUSYS related constants
35 ******************************************************************************/
36#define APUSYS_BASE (IO_PHYS + 0x09000000)
37#define APUSYS_CE_BASE (IO_PHYS + 0x090B0000)
Karl Li83f836c2024-11-14 16:18:54 +0800[diff] [blame^]38#define APU_AO_CTRL (IO_PHYS + 0x090F2000)
Karl Li9059a372024-11-14 16:04:49 +0800[diff] [blame]39#define APU_SEC_CON (IO_PHYS + 0x090F5000)
Karl Li31a0b872024-11-14 15:56:00 +0800[diff] [blame]40#define APUSYS_CTRL_DAPC_AO_BASE (IO_PHYS + 0x090FC000)
Karl Li0781f782024-11-14 15:46:27 +0800[diff] [blame]41
42#define APU_MBOX0 (0x4C200000)
43
Karl Li83f836c2024-11-14 16:18:54 +0800[diff] [blame^]44#define APU_MBOX0_SZ (0x100000)
45#define APU_INFRA_BASE (0x1002C000)
46#define APU_INFRA_SZ (0x1000)
47
Karl Li0781f782024-11-14 15:46:27 +0800[diff] [blame]48/*******************************************************************************
Gavin Liua65fadf2024-10-21 14:22:19 +0800[diff] [blame]49 * SPM related constants
50 ******************************************************************************/
51#define SPM_BASE (IO_PHYS + 0x0C004000)
52
53/*******************************************************************************
Cathy Xu4cb9f2a2024-02-27 17:07:31 +0800[diff] [blame]54 * GPIO related constants
55 ******************************************************************************/
56#define GPIO_BASE (IO_PHYS + 0x0002D000)
57#define RGU_BASE (IO_PHYS + 0x0C00B000)
58#define DRM_BASE (IO_PHYS + 0x0000D000)
59#define IOCFG_RT_BASE (IO_PHYS + 0x02000000)
60#define IOCFG_RM1_BASE (IO_PHYS + 0x02020000)
61#define IOCFG_RM2_BASE (IO_PHYS + 0x02040000)
62#define IOCFG_RB_BASE (IO_PHYS + 0x02060000)
63#define IOCFG_BM1_BASE (IO_PHYS + 0x02820000)
64#define IOCFG_BM2_BASE (IO_PHYS + 0x02840000)
65#define IOCFG_BM3_BASE (IO_PHYS + 0x02860000)
66#define IOCFG_LT_BASE (IO_PHYS + 0x03000000)
67#define IOCFG_LM1_BASE (IO_PHYS + 0x03020000)
68#define IOCFG_LM2_BASE (IO_PHYS + 0x03040000)
69#define IOCFG_LB1_BASE (IO_PHYS + 0x030f0000)
70#define IOCFG_LB2_BASE (IO_PHYS + 0x03110000)
71#define IOCFG_TM1_BASE (IO_PHYS + 0x03800000)
72#define IOCFG_TM2_BASE (IO_PHYS + 0x03820000)
73#define IOCFG_TM3_BASE (IO_PHYS + 0x03860000)
74
75/*******************************************************************************
Gavin Liua65fadf2024-10-21 14:22:19 +0800[diff] [blame]76 * UART related constants
77 ******************************************************************************/
78#define UART0_BASE (IO_PHYS + 0x06000000)
79#define UART_BAUDRATE (115200)
80
81/*******************************************************************************
82 * Infra IOMMU related constants
83 ******************************************************************************/
84#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
85#define INFRACFG_AO_MEM_BASE (IO_PHYS + 0x00404000)
86#define PERICFG_AO_BASE (IO_PHYS + 0x06630000)
87#define PERICFG_AO_REG_SIZE (0x1000)
88
89/*******************************************************************************
90 * GIC-600 & interrupt handling related constants
91 ******************************************************************************/
92/* Base MTK_platform compatible GIC memory map */
93#define BASE_GICD_BASE (MT_GIC_BASE)
94#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
95#define MTK_GIC_REG_SIZE 0x400000
96
97/*******************************************************************************
98 * MM IOMMU & SMI related constants
99 ******************************************************************************/
100#define SMI_LARB_0_BASE (IO_PHYS + 0x0c022000)
101#define SMI_LARB_1_BASE (IO_PHYS + 0x0c023000)
102#define SMI_LARB_2_BASE (IO_PHYS + 0x0c102000)
103#define SMI_LARB_3_BASE (IO_PHYS + 0x0c103000)
104#define SMI_LARB_4_BASE (IO_PHYS + 0x04013000)
105#define SMI_LARB_5_BASE (IO_PHYS + 0x04f02000)
106#define SMI_LARB_6_BASE (IO_PHYS + 0x04f03000)
107#define SMI_LARB_7_BASE (IO_PHYS + 0x04e04000)
108#define SMI_LARB_9_BASE (IO_PHYS + 0x05001000)
109#define SMI_LARB_10_BASE (IO_PHYS + 0x05120000)
110#define SMI_LARB_11A_BASE (IO_PHYS + 0x05230000)
111#define SMI_LARB_11B_BASE (IO_PHYS + 0x05530000)
112#define SMI_LARB_11C_BASE (IO_PHYS + 0x05630000)
113#define SMI_LARB_12_BASE (IO_PHYS + 0x05340000)
114#define SMI_LARB_13_BASE (IO_PHYS + 0x06001000)
115#define SMI_LARB_14_BASE (IO_PHYS + 0x06002000)
116#define SMI_LARB_15_BASE (IO_PHYS + 0x05140000)
117#define SMI_LARB_16A_BASE (IO_PHYS + 0x06008000)
118#define SMI_LARB_16B_BASE (IO_PHYS + 0x0600a000)
119#define SMI_LARB_17A_BASE (IO_PHYS + 0x06009000)
120#define SMI_LARB_17B_BASE (IO_PHYS + 0x0600b000)
121#define SMI_LARB_19_BASE (IO_PHYS + 0x0a010000)
122#define SMI_LARB_21_BASE (IO_PHYS + 0x0802e000)
123#define SMI_LARB_23_BASE (IO_PHYS + 0x0800d000)
124#define SMI_LARB_27_BASE (IO_PHYS + 0x07201000)
125#define SMI_LARB_28_BASE (IO_PHYS + 0x00000000)
126#define SMI_LARB_REG_RNG_SIZE (0x1000)
127
128/*******************************************************************************
129 * APMIXEDSYS related constants
130 ******************************************************************************/
131#define APMIXEDSYS (IO_PHYS + 0x0000C000)
132
133/*******************************************************************************
134 * VPPSYS related constants
135 ******************************************************************************/
136#define VPPSYS0_BASE (IO_PHYS + 0x04000000)
137#define VPPSYS1_BASE (IO_PHYS + 0x04f00000)
138
139/*******************************************************************************
140 * VDOSYS related constants
141 ******************************************************************************/
142#define VDOSYS0_BASE (IO_PHYS + 0x0C01D000)
143#define VDOSYS1_BASE (IO_PHYS + 0x0C100000)
144
145/*******************************************************************************
Mac Shen3e43d1d2024-12-10 14:15:20 +0800[diff] [blame]146 * DP related constants
147 ******************************************************************************/
148#define EDP_SEC_BASE (IO_PHYS + 0x2EC50000)
149#define DP_SEC_BASE (IO_PHYS + 0x2EC10000)
150#define EDP_SEC_SIZE (0x1000)
151#define DP_SEC_SIZE (0x1000)
152
153/*******************************************************************************
Gavin Liua65fadf2024-10-21 14:22:19 +0800[diff] [blame]154 * EMI MPU related constants
155 *******************************************************************************/
156#define EMI_MPU_BASE (IO_PHYS + 0x00428000)
157#define SUB_EMI_MPU_BASE (IO_PHYS + 0x00528000)
158
159/*******************************************************************************
160 * System counter frequency related constants
161 ******************************************************************************/
162#define SYS_COUNTER_FREQ_IN_HZ (13000000)
163#define SYS_COUNTER_FREQ_IN_MHZ (13)
164
165/*******************************************************************************
166 * Generic platform constants
167 ******************************************************************************/
168#define PLATFORM_STACK_SIZE (0x800)
169#define SOC_CHIP_ID U(0x8196)
170
171/*******************************************************************************
172 * Platform memory map related constants
173 ******************************************************************************/
174#define TZRAM_BASE (0x94600000)
175#define TZRAM_SIZE (0x00200000)
176
177/*******************************************************************************
178 * BL31 specific defines.
179 ******************************************************************************/
180/*
181 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
182 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a
183 * little space for growth.
184 */
185#define BL31_BASE (TZRAM_BASE + 0x1000)
186#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
187
188/*******************************************************************************
189 * Platform specific page table and MMU setup constants
190 ******************************************************************************/
191#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39)
192#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39)
193#define MAX_XLAT_TABLES (128)
194#define MAX_MMAP_REGIONS (512)
195
196/*******************************************************************************
197 * CPU PM definitions
198 *******************************************************************************/
199#define PLAT_CPU_PM_B_BUCK_ISO_ID (6)
200#define PLAT_CPU_PM_ILDO_ID (6)
201#define CPU_IDLE_SRAM_BASE (0x11B000)
202#define CPU_IDLE_SRAM_SIZE (0x1000)
203
204/*******************************************************************************
205 * SYSTIMER related definitions
206 ******************************************************************************/
207#define SYSTIMER_BASE (0x1C400000)
208
209#endif /* PLATFORM_DEF_H */