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review.trustedfirmware.org / TF-A / trusted-firmware-a / d323af9e3d903d981b42f954844a95a6bfef91ab / . / plat / arm / board / common / board_css_common.c
blob: 40b1a275af6e08a29047dbcc3523eced777df5bc [file] [log] [blame]
Dan Handleyb4315302015-03-19 18:58:55 +0000[diff] [blame]1/*
Roberto Vargas638b0342018-01-05 16:00:05 +0000[diff] [blame]2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Dan Handleyb4315302015-03-19 18:58:55 +0000[diff] [blame]3 *
dp-arm82cb2c12017-05-03 09:38:09 +0100[diff] [blame]4 * SPDX-License-Identifier: BSD-3-Clause
Dan Handleyb4315302015-03-19 18:58:55 +0000[diff] [blame]5 */
6#include <arm_def.h>
7#include <plat_arm.h>
8
9/*
Sandrine Bailleuxb5fa6562016-05-18 16:11:47 +0100[diff] [blame]10 * Table of memory regions for different BL stages to map using the MMU.
11 * This doesn't include Trusted SRAM as arm_setup_page_tables() already
12 * takes care of mapping it.
Dan Handleyb4315302015-03-19 18:58:55 +0000[diff] [blame]13 */
Masahiro Yamada3d8256b2016-12-25 23:36:24 +0900[diff] [blame]14#ifdef IMAGE_BL1
Dan Handleyb4315302015-03-19 18:58:55 +0000[diff] [blame]15const mmap_region_t plat_arm_mmap[] = {
16 ARM_MAP_SHARED_RAM,
Soby Mathew7b569282018-03-07 11:32:04 +0000[diff] [blame]17 V2M_MAP_FLASH0_RW,
Dan Handleyb4315302015-03-19 18:58:55 +0000[diff] [blame]18 V2M_MAP_IOFPGA,
19 CSS_MAP_DEVICE,
20 SOC_CSS_MAP_DEVICE,
Yatharth Kochar436223d2015-10-11 14:14:55 +0100[diff] [blame]21#if TRUSTED_BOARD_BOOT
Sandrine Bailleux284c3d62017-05-26 15:48:10 +0100[diff] [blame]22 /* Map DRAM to authenticate NS_BL2U image. */
Yatharth Kochar436223d2015-10-11 14:14:55 +0100[diff] [blame]23 ARM_MAP_NS_DRAM1,
24#endif
Dan Handleyb4315302015-03-19 18:58:55 +0000[diff] [blame]25 {0}
26};
27#endif
Masahiro Yamada3d8256b2016-12-25 23:36:24 +0900[diff] [blame]28#ifdef IMAGE_BL2
Dan Handleyb4315302015-03-19 18:58:55 +0000[diff] [blame]29const mmap_region_t plat_arm_mmap[] = {
30 ARM_MAP_SHARED_RAM,
Soby Mathew7b569282018-03-07 11:32:04 +0000[diff] [blame]31 V2M_MAP_FLASH0_RW,
Roberto Vargasf1454032017-08-03 09:16:43 +0100[diff] [blame]32#ifdef PLAT_ARM_MEM_PROT_ADDR
33 ARM_V2M_MAP_MEM_PROTECT,
34#endif
Dan Handleyb4315302015-03-19 18:58:55 +0000[diff] [blame]35 V2M_MAP_IOFPGA,
36 CSS_MAP_DEVICE,
37 SOC_CSS_MAP_DEVICE,
38 ARM_MAP_NS_DRAM1,
Roberto Vargasb09ba052017-08-08 11:27:20 +0100[diff] [blame]39#ifdef AARCH64
40 ARM_MAP_DRAM2,
41#endif
Sandrine Bailleux3eb2d672017-08-30 10:59:22 +0100[diff] [blame]42#ifdef SPD_tspd
Dan Handleyb4315302015-03-19 18:58:55 +0000[diff] [blame]43 ARM_MAP_TSP_SEC_MEM,
Sandrine Bailleux3eb2d672017-08-30 10:59:22 +0100[diff] [blame]44#endif
Summer Qin54661cd2017-04-24 16:49:28 +0100[diff] [blame]45#ifdef SPD_opteed
Soby Mathewb3ba6fd2017-09-01 13:43:50 +0100[diff] [blame]46 ARM_MAP_OPTEE_CORE_MEM,
Summer Qin54661cd2017-04-24 16:49:28 +0100[diff] [blame]47 ARM_OPTEE_PAGEABLE_LOAD_MEM,
48#endif
Dan Handleyb4315302015-03-19 18:58:55 +0000[diff] [blame]49 {0}
50};
51#endif
Masahiro Yamada3d8256b2016-12-25 23:36:24 +0900[diff] [blame]52#ifdef IMAGE_BL2U
Yatharth Kochardcda29f2015-10-14 15:28:11 +0100[diff] [blame]53const mmap_region_t plat_arm_mmap[] = {
54 ARM_MAP_SHARED_RAM,
55 CSS_MAP_DEVICE,
Daniel Boulbyd323af92018-07-06 16:54:44 +0100[diff] [blame^]56 CSS_MAP_SCP_BL2U,
57 V2M_MAP_IOFPGA,
Yatharth Kochardcda29f2015-10-14 15:28:11 +0100[diff] [blame]58 SOC_CSS_MAP_DEVICE,
59 {0}
60};
61#endif
Masahiro Yamada3d8256b2016-12-25 23:36:24 +0900[diff] [blame]62#ifdef IMAGE_BL31
Dan Handleyb4315302015-03-19 18:58:55 +0000[diff] [blame]63const mmap_region_t plat_arm_mmap[] = {
64 ARM_MAP_SHARED_RAM,
65 V2M_MAP_IOFPGA,
66 CSS_MAP_DEVICE,
Roberto Vargasf1454032017-08-03 09:16:43 +0100[diff] [blame]67#ifdef PLAT_ARM_MEM_PROT_ADDR
68 ARM_V2M_MAP_MEM_PROTECT,
69#endif
Dan Handleyb4315302015-03-19 18:58:55 +0000[diff] [blame]70 SOC_CSS_MAP_DEVICE,
71 {0}
72};
73#endif
Masahiro Yamada3d8256b2016-12-25 23:36:24 +0900[diff] [blame]74#ifdef IMAGE_BL32
Dan Handleyb4315302015-03-19 18:58:55 +0000[diff] [blame]75const mmap_region_t plat_arm_mmap[] = {
Yatharth Kochar6f249342016-11-14 12:00:41 +0000[diff] [blame]76#ifdef AARCH32
77 ARM_MAP_SHARED_RAM,
Roberto Vargas638b0342018-01-05 16:00:05 +0000[diff] [blame]78#ifdef PLAT_ARM_MEM_PROT_ADDR
79 ARM_V2M_MAP_MEM_PROTECT,
80#endif
Yatharth Kochar6f249342016-11-14 12:00:41 +0000[diff] [blame]81#endif
Dan Handleyb4315302015-03-19 18:58:55 +0000[diff] [blame]82 V2M_MAP_IOFPGA,
83 CSS_MAP_DEVICE,
84 SOC_CSS_MAP_DEVICE,
85 {0}
86};
87#endif
88
89ARM_CASSERT_MMAP