blob: 84bba18e6be62d8db5535a63dd8a6c5a809b5851 [file] [log] [blame]
Paul Beesley8aa05052019-03-07 15:47:15 +00001Firmware Design
Douglas Raillard6f625742017-06-28 15:23:03 +01003
Dan Handley4def07d2018-03-01 18:44:00 +00004Trusted Firmware-A (TF-A) implements a subset of the Trusted Board Boot
Paul Beesley34760952019-04-12 14:19:42 +01005Requirements (TBBR) Platform Design Document (PDD) for Arm reference
8The TBB sequence starts when the platform is powered on and runs up
Douglas Raillard6f625742017-06-28 15:23:03 +01009to the stage where it hands-off control to firmware running in the normal
10world in DRAM. This is the cold boot path.
Paul Beesley34760952019-04-12 14:19:42 +010012TF-A also implements the `Power State Coordination Interface PDD`_ as a
Dan Handley4def07d2018-03-01 18:44:00 +000013runtime service. PSCI is the interface from normal world software to firmware
14implementing power management use-cases (for example, secondary CPU boot,
15hotplug and idle). Normal world software can access TF-A runtime services via
16the Arm SMC (Secure Monitor Call) instruction. The SMC instruction must be
Paul Beesley34760952019-04-12 14:19:42 +010017used as mandated by the SMC Calling Convention (`SMCCC`_).
Douglas Raillard6f625742017-06-28 15:23:03 +010018
Dan Handley4def07d2018-03-01 18:44:00 +000019TF-A implements a framework for configuring and managing interrupts generated
20in either security state. The details of the interrupt management framework
Paul Beesley34760952019-04-12 14:19:42 +010021and its design can be found in :ref:`Interrupt Management Framework`.
Douglas Raillard6f625742017-06-28 15:23:03 +010022
Dan Handley4def07d2018-03-01 18:44:00 +000023TF-A also implements a library for setting up and managing the translation
Paul Beesley34760952019-04-12 14:19:42 +010024tables. The details of this library can be found in
25:ref:`Translation (XLAT) Tables Library`.
Antonio Nino Diaz6feb9e82017-05-23 11:49:22 +010026
Dan Handley4def07d2018-03-01 18:44:00 +000027TF-A can be built to support either AArch64 or AArch32 execution state.
Douglas Raillard6f625742017-06-28 15:23:03 +010028
Zelalem Aweke7446c262021-10-21 13:59:45 -050029.. note::
31 The descriptions in this chapter are for the Arm TrustZone architecture.
32 For changes to the firmware design for the
33 `Arm Confidential Compute Architecture (Arm CCA)`_ please refer to the
34 chapter :ref:`Realm Management Extension (RME)`.
Douglas Raillard6f625742017-06-28 15:23:03 +010036Cold boot
39The cold boot path starts when the platform is physically turned on. If
40``COLD_BOOT_SINGLE_CPU=0``, one of the CPUs released from reset is chosen as the
41primary CPU, and the remaining CPUs are considered secondary CPUs. The primary
42CPU is chosen through platform-specific means. The cold boot path is mainly
43executed by the primary CPU, other than essential CPU initialization executed by
44all CPUs. The secondary CPUs are kept in a safe platform-specific state until
45the primary CPU has performed enough initialization to boot them.
Paul Beesley34760952019-04-12 14:19:42 +010047Refer to the :ref:`CPU Reset` for more information on the effect of the
Douglas Raillard6f625742017-06-28 15:23:03 +010048``COLD_BOOT_SINGLE_CPU`` platform build option.
Dan Handley4def07d2018-03-01 18:44:00 +000050The cold boot path in this implementation of TF-A depends on the execution
51state. For AArch64, it is divided into five steps (in order of execution):
Douglas Raillard6f625742017-06-28 15:23:03 +010052
53- Boot Loader stage 1 (BL1) *AP Trusted ROM*
54- Boot Loader stage 2 (BL2) *Trusted Boot Firmware*
55- Boot Loader stage 3-1 (BL31) *EL3 Runtime Software*
56- Boot Loader stage 3-2 (BL32) *Secure-EL1 Payload* (optional)
57- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware*
59For AArch32, it is divided into four steps (in order of execution):
61- Boot Loader stage 1 (BL1) *AP Trusted ROM*
62- Boot Loader stage 2 (BL2) *Trusted Boot Firmware*
63- Boot Loader stage 3-2 (BL32) *EL3 Runtime Software*
64- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware*
Dan Handley4def07d2018-03-01 18:44:00 +000066Arm development platforms (Fixed Virtual Platforms (FVPs) and Juno) implement a
Douglas Raillard6f625742017-06-28 15:23:03 +010067combination of the following types of memory regions. Each bootloader stage uses
68one or more of these memory regions.
70- Regions accessible from both non-secure and secure states. For example,
71 non-trusted SRAM, ROM and DRAM.
72- Regions accessible from only the secure state. For example, trusted SRAM and
73 ROM. The FVPs also implement the trusted DRAM which is statically
74 configured. Additionally, the Base FVPs and Juno development platform
75 configure the TrustZone Controller (TZC) to create a region in the DRAM
76 which is accessible only from the secure state.
78The sections below provide the following details:
Soby Mathewb2a68f82018-02-16 14:52:52 +000080- dynamic configuration of Boot Loader stages
Douglas Raillard6f625742017-06-28 15:23:03 +010081- initialization and execution of the first three stages during cold boot
82- specification of the EL3 Runtime Software (BL31 for AArch64 and BL32 for
83 AArch32) entrypoint requirements for use by alternative Trusted Boot
84 Firmware in place of the provided BL1 and BL2
Soby Mathewb2a68f82018-02-16 14:52:52 +000086Dynamic Configuration during cold boot
89Each of the Boot Loader stages may be dynamically configured if required by the
90platform. The Boot Loader stage may optionally specify a firmware
91configuration file and/or hardware configuration file as listed below:
Manish V Badarkhe089fc622020-06-13 09:42:28 +010093- FW_CONFIG - The firmware configuration file. Holds properties shared across
94 all BLx images.
95 An example is the "dtb-registry" node, which contains the information about
96 the other device tree configurations (load-address, size, image_id).
Soby Mathewb2a68f82018-02-16 14:52:52 +000097- HW_CONFIG - The hardware configuration file. Can be shared by all Boot Loader
98 stages and also by the Normal World Rich OS.
99- TB_FW_CONFIG - Trusted Boot Firmware configuration file. Shared between BL1
100 and BL2.
101- SOC_FW_CONFIG - SoC Firmware configuration file. Used by BL31.
102- TOS_FW_CONFIG - Trusted OS Firmware configuration file. Used by Trusted OS
103 (BL32).
104- NT_FW_CONFIG - Non Trusted Firmware configuration file. Used by Non-trusted
105 firmware (BL33).
107The Arm development platforms use the Flattened Device Tree format for the
108dynamic configuration files.
110Each Boot Loader stage can pass up to 4 arguments via registers to the next
111stage. BL2 passes the list of the next images to execute to the *EL3 Runtime
112Software* (BL31 for AArch64 and BL32 for AArch32) via `arg0`. All the other
113arguments are platform defined. The Arm development platforms use the following
116- BL1 passes the address of a meminfo_t structure to BL2 via ``arg1``. This
117 structure contains the memory layout available to BL2.
118- When dynamic configuration files are present, the firmware configuration for
119 the next Boot Loader stage is populated in the first available argument and
120 the generic hardware configuration is passed the next available argument.
121 For example,
Manish V Badarkhe089fc622020-06-13 09:42:28 +0100123 - FW_CONFIG is loaded by BL1, then its address is passed in ``arg0`` to BL2.
124 - TB_FW_CONFIG address is retrieved by BL2 from FW_CONFIG device tree.
Soby Mathewb2a68f82018-02-16 14:52:52 +0000125 - If HW_CONFIG is loaded by BL1, then its address is passed in ``arg2`` to
126 BL2. Note, ``arg1`` is already used for meminfo_t.
127 - If SOC_FW_CONFIG is loaded by BL2, then its address is passed in ``arg1``
128 to BL31. Note, ``arg0`` is used to pass the list of executable images.
129 - Similarly, if HW_CONFIG is loaded by BL1 or BL2, then its address is
130 passed in ``arg2`` to BL31.
131 - For other BL3x images, if the firmware configuration file is loaded by
132 BL2, then its address is passed in ``arg0`` and if HW_CONFIG is loaded
133 then its address is passed in ``arg1``.
Manish V Badarkheb4a87832022-04-12 21:11:56 +0100134 - In case of the Arm FVP platform, FW_CONFIG address passed in ``arg1`` to
135 BL31/SP_MIN, and the SOC_FW_CONFIG and HW_CONFIG details are retrieved
136 from FW_CONFIG device tree.
Soby Mathewb2a68f82018-02-16 14:52:52 +0000137
Douglas Raillard6f625742017-06-28 15:23:03 +0100138BL1
141This stage begins execution from the platform's reset vector at EL3. The reset
142address is platform dependent but it is usually located in a Trusted ROM area.
143The BL1 data section is copied to trusted SRAM at runtime.
Dan Handley4def07d2018-03-01 18:44:00 +0000145On the Arm development platforms, BL1 code starts execution from the reset
Douglas Raillard6f625742017-06-28 15:23:03 +0100146vector defined by the constant ``BL1_RO_BASE``. The BL1 data section is copied
147to the top of trusted SRAM as defined by the constant ``BL1_RW_BASE``.
149The functionality implemented by this stage is as follows.
151Determination of boot path
154Whenever a CPU is released from reset, BL1 needs to distinguish between a warm
155boot and a cold boot. This is done using platform-specific mechanisms (see the
Paul Beesley34760952019-04-12 14:19:42 +0100156``plat_get_my_entrypoint()`` function in the :ref:`Porting Guide`). In the case
157of a warm boot, a CPU is expected to continue execution from a separate
Douglas Raillard6f625742017-06-28 15:23:03 +0100158entrypoint. In the case of a cold boot, the secondary CPUs are placed in a safe
159platform-specific state (see the ``plat_secondary_cold_boot_setup()`` function in
Paul Beesley34760952019-04-12 14:19:42 +0100160the :ref:`Porting Guide`) while the primary CPU executes the remaining cold boot
161path as described in the following sections.
Douglas Raillard6f625742017-06-28 15:23:03 +0100162
163This step only applies when ``PROGRAMMABLE_RESET_ADDRESS=0``. Refer to the
Paul Beesley34760952019-04-12 14:19:42 +0100164:ref:`CPU Reset` for more information on the effect of the
Douglas Raillard6f625742017-06-28 15:23:03 +0100165``PROGRAMMABLE_RESET_ADDRESS`` platform build option.
167Architectural initialization
170BL1 performs minimal architectural initialization as follows.
172- Exception vectors
174 BL1 sets up simple exception vectors for both synchronous and asynchronous
175 exceptions. The default behavior upon receiving an exception is to populate
176 a status code in the general purpose register ``X0/R0`` and call the
Paul Beesley34760952019-04-12 14:19:42 +0100177 ``plat_report_exception()`` function (see the :ref:`Porting Guide`). The
178 status code is one of:
Douglas Raillard6f625742017-06-28 15:23:03 +0100179
180 For AArch64:
182 ::
184 0x0 : Synchronous exception from Current EL with SP_EL0
185 0x1 : IRQ exception from Current EL with SP_EL0
186 0x2 : FIQ exception from Current EL with SP_EL0
187 0x3 : System Error exception from Current EL with SP_EL0
188 0x4 : Synchronous exception from Current EL with SP_ELx
189 0x5 : IRQ exception from Current EL with SP_ELx
190 0x6 : FIQ exception from Current EL with SP_ELx
191 0x7 : System Error exception from Current EL with SP_ELx
192 0x8 : Synchronous exception from Lower EL using aarch64
193 0x9 : IRQ exception from Lower EL using aarch64
194 0xa : FIQ exception from Lower EL using aarch64
195 0xb : System Error exception from Lower EL using aarch64
196 0xc : Synchronous exception from Lower EL using aarch32
197 0xd : IRQ exception from Lower EL using aarch32
198 0xe : FIQ exception from Lower EL using aarch32
199 0xf : System Error exception from Lower EL using aarch32
201 For AArch32:
203 ::
205 0x10 : User mode
206 0x11 : FIQ mode
207 0x12 : IRQ mode
208 0x13 : SVC mode
209 0x16 : Monitor mode
210 0x17 : Abort mode
211 0x1a : Hypervisor mode
212 0x1b : Undefined mode
213 0x1f : System mode
Dan Handley4def07d2018-03-01 18:44:00 +0000215 The ``plat_report_exception()`` implementation on the Arm FVP port programs
Douglas Raillard6f625742017-06-28 15:23:03 +0100216 the Versatile Express System LED register in the following format to
Paul Beesley8aabea32019-01-11 18:26:51 +0000217 indicate the occurrence of an unexpected exception:
Douglas Raillard6f625742017-06-28 15:23:03 +0100218
219 ::
221 SYS_LED[0] - Security state (Secure=0/Non-Secure=1)
222 SYS_LED[2:1] - Exception Level (EL3=0x3, EL2=0x2, EL1=0x1, EL0=0x0)
223 For AArch32 it is always 0x0
224 SYS_LED[7:3] - Exception Class (Sync/Async & origin). This is the value
225 of the status code
227 A write to the LED register reflects in the System LEDs (S6LED0..7) in the
228 CLCD window of the FVP.
230 BL1 does not expect to receive any exceptions other than the SMC exception.
231 For the latter, BL1 installs a simple stub. The stub expects to receive a
232 limited set of SMC types (determined by their function IDs in the general
233 purpose register ``X0/R0``):
235 - ``BL1_SMC_RUN_IMAGE``: This SMC is raised by BL2 to make BL1 pass control
236 to EL3 Runtime Software.
Paul Beesley34760952019-04-12 14:19:42 +0100237 - All SMCs listed in section "BL1 SMC Interface" in the :ref:`Firmware Update (FWU)`
Douglas Raillard6f625742017-06-28 15:23:03 +0100238 Design Guide are supported for AArch64 only. These SMCs are currently
239 not supported when BL1 is built for AArch32.
241 Any other SMC leads to an assertion failure.
243- CPU initialization
245 BL1 calls the ``reset_handler()`` function which in turn calls the CPU
246 specific reset handler function (see the section: "CPU specific operations
247 framework").
249- Control register setup (for AArch64)
251 - ``SCTLR_EL3``. Instruction cache is enabled by setting the ``SCTLR_EL3.I``
252 bit. Alignment and stack alignment checking is enabled by setting the
253 ``SCTLR_EL3.A`` and ``SCTLR_EL3.SA`` bits. Exception endianness is set to
254 little-endian by clearing the ``SCTLR_EL3.EE`` bit.
256 - ``SCR_EL3``. The register width of the next lower exception level is set
257 to AArch64 by setting the ``SCR.RW`` bit. The ``SCR.EA`` bit is set to trap
258 both External Aborts and SError Interrupts in EL3. The ``SCR.SIF`` bit is
259 also set to disable instruction fetches from Non-secure memory when in
260 secure state.
262 - ``CPTR_EL3``. Accesses to the ``CPACR_EL1`` register from EL1 or EL2, or the
263 ``CPTR_EL2`` register from EL2 are configured to not trap to EL3 by
264 clearing the ``CPTR_EL3.TCPAC`` bit. Access to the trace functionality is
265 configured not to trap to EL3 by clearing the ``CPTR_EL3.TTA`` bit.
266 Instructions that access the registers associated with Floating Point
267 and Advanced SIMD execution are configured to not trap to EL3 by
268 clearing the ``CPTR_EL3.TFP`` bit.
270 - ``DAIF``. The SError interrupt is enabled by clearing the SError interrupt
271 mask bit.
273 - ``MDCR_EL3``. The trap controls, ``MDCR_EL3.TDOSA``, ``MDCR_EL3.TDA`` and
274 ``MDCR_EL3.TPM``, are set so that accesses to the registers they control
275 do not trap to EL3. AArch64 Secure self-hosted debug is disabled by
276 setting the ``MDCR_EL3.SDD`` bit. Also ``MDCR_EL3.SPD32`` is set to
277 disable AArch32 Secure self-hosted privileged debug from S-EL1.
279- Control register setup (for AArch32)
281 - ``SCTLR``. Instruction cache is enabled by setting the ``SCTLR.I`` bit.
282 Alignment checking is enabled by setting the ``SCTLR.A`` bit.
283 Exception endianness is set to little-endian by clearing the
284 ``SCTLR.EE`` bit.
286 - ``SCR``. The ``SCR.SIF`` bit is set to disable instruction fetches from
287 Non-secure memory when in secure state.
289 - ``CPACR``. Allow execution of Advanced SIMD instructions at PL0 and PL1,
290 by clearing the ``CPACR.ASEDIS`` bit. Access to the trace functionality
291 is configured not to trap to undefined mode by clearing the
292 ``CPACR.TRCDIS`` bit.
294 - ``NSACR``. Enable non-secure access to Advanced SIMD functionality and
295 system register access to implemented trace registers.
297 - ``FPEXC``. Enable access to the Advanced SIMD and floating-point
298 functionality from all Exception levels.
300 - ``CPSR.A``. The Asynchronous data abort interrupt is enabled by clearing
301 the Asynchronous data abort interrupt mask bit.
303 - ``SDCR``. The ``SDCR.SPD`` field is set to disable AArch32 Secure
304 self-hosted privileged debug.
306Platform initialization
Dan Handley4def07d2018-03-01 18:44:00 +0000309On Arm platforms, BL1 performs the following platform initializations:
Douglas Raillard6f625742017-06-28 15:23:03 +0100310
311- Enable the Trusted Watchdog.
312- Initialize the console.
313- Configure the Interconnect to enable hardware coherency.
314- Enable the MMU and map the memory it needs to access.
315- Configure any required platform storage to load the next bootloader image
316 (BL2).
Soby Mathewb2a68f82018-02-16 14:52:52 +0000317- If the BL1 dynamic configuration file, ``TB_FW_CONFIG``, is available, then
318 load it to the platform defined address and make it available to BL2 via
319 ``arg0``.
Soby Mathew3208edc2018-06-11 16:40:36 +0100320- Configure the system timer and program the `CNTFRQ_EL0` for use by NS-BL1U
321 and NS-BL2U firmware update images.
Douglas Raillard6f625742017-06-28 15:23:03 +0100322
323Firmware Update detection and execution
326After performing platform setup, BL1 common code calls
Paul Beesley34760952019-04-12 14:19:42 +0100327``bl1_plat_get_next_image_id()`` to determine if :ref:`Firmware Update (FWU)` is
328required or to proceed with the normal boot process. If the platform code
329returns ``BL2_IMAGE_ID`` then the normal boot sequence is executed as described
330in the next section, else BL1 assumes that :ref:`Firmware Update (FWU)` is
331required and execution passes to the first image in the
332:ref:`Firmware Update (FWU)` process. In either case, BL1 retrieves a descriptor
333of the next image by calling ``bl1_plat_get_image_desc()``. The image descriptor
334contains an ``entry_point_info_t`` structure, which BL1 uses to initialize the
335execution state of the next image.
Douglas Raillard6f625742017-06-28 15:23:03 +0100336
337BL2 image load and execution
340In the normal boot flow, BL1 execution continues as follows:
342#. BL1 prints the following string from the primary CPU to indicate successful
343 execution of the BL1 stage:
345 ::
347 "Booting Trusted Firmware"
Soby Mathewb2a68f82018-02-16 14:52:52 +0000349#. BL1 loads a BL2 raw binary image from platform storage, at a
350 platform-specific base address. Prior to the load, BL1 invokes
351 ``bl1_plat_handle_pre_image_load()`` which allows the platform to update or
352 use the image information. If the BL2 image file is not present or if
Douglas Raillard6f625742017-06-28 15:23:03 +0100353 there is not enough free trusted SRAM the following error message is
354 printed:
356 ::
358 "Failed to load BL2 firmware."
Soby Mathewb2a68f82018-02-16 14:52:52 +0000360#. BL1 invokes ``bl1_plat_handle_post_image_load()`` which again is intended
361 for platforms to take further action after image load. This function must
362 populate the necessary arguments for BL2, which may also include the memory
363 layout. Further description of the memory layout can be found later
364 in this document.
Douglas Raillard6f625742017-06-28 15:23:03 +0100365
366#. BL1 passes control to the BL2 image at Secure EL1 (for AArch64) or at
367 Secure SVC mode (for AArch32), starting from its load address.
Douglas Raillard6f625742017-06-28 15:23:03 +0100369BL2
372BL1 loads and passes control to BL2 at Secure-EL1 (for AArch64) or at Secure
373SVC mode (for AArch32) . BL2 is linked against and loaded at a platform-specific
374base address (more information can be found later in this document).
375The functionality implemented by BL2 is as follows.
377Architectural initialization
380For AArch64, BL2 performs the minimal architectural initialization required
Dan Handley4def07d2018-03-01 18:44:00 +0000381for subsequent stages of TF-A and normal world software. EL1 and EL0 are given
Peng Fan093ba622020-08-21 10:47:17 +0800382access to Floating Point and Advanced SIMD registers by setting the
Dan Handley4def07d2018-03-01 18:44:00 +0000383``CPACR.FPEN`` bits.
Douglas Raillard6f625742017-06-28 15:23:03 +0100384
385For AArch32, the minimal architectural initialization required for subsequent
Dan Handley4def07d2018-03-01 18:44:00 +0000386stages of TF-A and normal world software is taken care of in BL1 as both BL1
387and BL2 execute at PL1.
Douglas Raillard6f625742017-06-28 15:23:03 +0100388
389Platform initialization
Dan Handley4def07d2018-03-01 18:44:00 +0000392On Arm platforms, BL2 performs the following platform initializations:
Douglas Raillard6f625742017-06-28 15:23:03 +0100393
394- Initialize the console.
395- Configure any required platform storage to allow loading further bootloader
396 images.
397- Enable the MMU and map the memory it needs to access.
398- Perform platform security setup to allow access to controlled components.
399- Reserve some memory for passing information to the next bootloader image
400 EL3 Runtime Software and populate it.
401- Define the extents of memory available for loading each subsequent
402 bootloader image.
Soby Mathewb2a68f82018-02-16 14:52:52 +0000403- If BL1 has passed TB_FW_CONFIG dynamic configuration file in ``arg0``,
404 then parse it.
Douglas Raillard6f625742017-06-28 15:23:03 +0100405
406Image loading in BL2
Roberto Vargased51b512018-09-24 17:20:48 +0100409BL2 generic code loads the images based on the list of loadable images
410provided by the platform. BL2 passes the list of executable images
411provided by the platform to the next handover BL image.
Douglas Raillard6f625742017-06-28 15:23:03 +0100412
Soby Mathewb2a68f82018-02-16 14:52:52 +0000413The list of loadable images provided by the platform may also contain
414dynamic configuration files. The files are loaded and can be parsed as
415needed in the ``bl2_plat_handle_post_image_load()`` function. These
416configuration files can be passed to next Boot Loader stages as arguments
417by updating the corresponding entrypoint information in this function.
Sandrine Bailleuxf3cacad2019-02-08 15:26:36 +0100419SCP_BL2 (System Control Processor Firmware) image load
Douglas Raillard6f625742017-06-28 15:23:03 +0100421
422Some systems have a separate System Control Processor (SCP) for power, clock,
Sandrine Bailleuxf3cacad2019-02-08 15:26:36 +0100423reset and system control. BL2 loads the optional SCP_BL2 image from platform
Douglas Raillard6f625742017-06-28 15:23:03 +0100424storage into a platform-specific region of secure memory. The subsequent
Sandrine Bailleuxf3cacad2019-02-08 15:26:36 +0100425handling of SCP_BL2 is platform specific. For example, on the Juno Arm
Douglas Raillard6f625742017-06-28 15:23:03 +0100426development platform port the image is transferred into SCP's internal memory
427using the Boot Over MHU (BOM) protocol after being loaded in the trusted SRAM
Sandrine Bailleuxf3cacad2019-02-08 15:26:36 +0100428memory. The SCP executes SCP_BL2 and signals to the Application Processor (AP)
Douglas Raillard6f625742017-06-28 15:23:03 +0100429for BL2 execution to continue.
431EL3 Runtime Software image load
434BL2 loads the EL3 Runtime Software image from platform storage into a platform-
435specific address in trusted SRAM. If there is not enough memory to load the
Roberto Vargased51b512018-09-24 17:20:48 +0100436image or image is missing it leads to an assertion failure.
Douglas Raillard6f625742017-06-28 15:23:03 +0100437
438AArch64 BL32 (Secure-EL1 Payload) image load
441BL2 loads the optional BL32 image from platform storage into a platform-
442specific region of secure memory. The image executes in the secure world. BL2
443relies on BL31 to pass control to the BL32 image, if present. Hence, BL2
444populates a platform-specific area of memory with the entrypoint/load-address
445of the BL32 image. The value of the Saved Processor Status Register (``SPSR``)
446for entry into BL32 is not determined by BL2, it is initialized by the
447Secure-EL1 Payload Dispatcher (see later) within BL31, which is responsible for
448managing interaction with BL32. This information is passed to BL31.
450BL33 (Non-trusted Firmware) image load
453BL2 loads the BL33 image (e.g. UEFI or other test or boot software) from
454platform storage into non-secure memory as defined by the platform.
456BL2 relies on EL3 Runtime Software to pass control to BL33 once secure state
457initialization is complete. Hence, BL2 populates a platform-specific area of
458memory with the entrypoint and Saved Program Status Register (``SPSR``) of the
459normal world software image. The entrypoint is the load address of the BL33
460image. The ``SPSR`` is determined as specified in Section 5.13 of the
Paul Beesley34760952019-04-12 14:19:42 +0100461`Power State Coordination Interface PDD`_. This information is passed to the
462EL3 Runtime Software.
Douglas Raillard6f625742017-06-28 15:23:03 +0100463
464AArch64 BL31 (EL3 Runtime Software) execution
467BL2 execution continues as follows:
469#. BL2 passes control back to BL1 by raising an SMC, providing BL1 with the
470 BL31 entrypoint. The exception is handled by the SMC exception handler
471 installed by BL1.
473#. BL1 turns off the MMU and flushes the caches. It clears the
474 ``SCTLR_EL3.M/I/C`` bits, flushes the data cache to the point of coherency
475 and invalidates the TLBs.
477#. BL1 passes control to BL31 at the specified entrypoint at EL3.
Roberto Vargas4cd17692017-11-20 13:36:10 +0000479Running BL2 at EL3 execution level
Dan Handley4def07d2018-03-01 18:44:00 +0000482Some platforms have a non-TF-A Boot ROM that expects the next boot stage
483to execute at EL3. On these platforms, TF-A BL1 is a waste of memory
484as its only purpose is to ensure TF-A BL2 is entered at S-EL1. To avoid
Roberto Vargas4cd17692017-11-20 13:36:10 +0000485this waste, a special mode enables BL2 to execute at EL3, which allows
Dan Handley4def07d2018-03-01 18:44:00 +0000486a non-TF-A Boot ROM to load and jump directly to BL2. This mode is selected
Roberto Vargas4cd17692017-11-20 13:36:10 +0000487when the build flag BL2_AT_EL3 is enabled. The main differences in this
488mode are:
490#. BL2 includes the reset code and the mailbox mechanism to differentiate
491 cold boot and warm boot. It runs at EL3 doing the arch
492 initialization required for EL3.
494#. BL2 does not receive the meminfo information from BL1 anymore. This
495 information can be passed by the Boot ROM or be internal to the
496 BL2 image.
498#. Since BL2 executes at EL3, BL2 jumps directly to the next image,
499 instead of invoking the RUN_IMAGE SMC call.
502We assume 3 different types of BootROM support on the platform:
504#. The Boot ROM always jumps to the same address, for both cold
505 and warm boot. In this case, we will need to keep a resident part
506 of BL2 whose memory cannot be reclaimed by any other image. The
507 linker script defines the symbols __TEXT_RESIDENT_START__ and
508 __TEXT_RESIDENT_END__ that allows the platform to configure
509 correctly the memory map.
510#. The platform has some mechanism to indicate the jump address to the
511 Boot ROM. Platform code can then program the jump address with
512 psci_warmboot_entrypoint during cold boot.
513#. The platform has some mechanism to program the reset address using
514 the PROGRAMMABLE_RESET_ADDRESS feature. Platform code can then
515 program the reset address with psci_warmboot_entrypoint during
516 cold boot, bypassing the boot ROM for warm boot.
518In the last 2 cases, no part of BL2 needs to remain resident at
519runtime. In the first 2 cases, we expect the Boot ROM to be able to
520differentiate between warm and cold boot, to avoid loading BL2 again
521during warm boot.
523This functionality can be tested with FVP loading the image directly
524in memory and changing the address where the system jumps at reset.
525For example:
Dimitris Papastamos42be6fc2018-06-11 11:07:58 +0100527 -C cluster0.cpu0.RVBAR=0x4022000
528 --data cluster0.cpu0=bl2.bin@0x4022000
Roberto Vargas4cd17692017-11-20 13:36:10 +0000529
530With this configuration, FVP is like a platform of the first case,
531where the Boot ROM jumps always to the same address. For simplification,
532BL32 is loaded in DRAM in this case, to avoid other images reclaiming
533BL2 memory.
Douglas Raillard6f625742017-06-28 15:23:03 +0100536AArch64 BL31
539The image for this stage is loaded by BL2 and BL1 passes control to BL31 at
540EL3. BL31 executes solely in trusted SRAM. BL31 is linked against and
541loaded at a platform-specific base address (more information can be found later
542in this document). The functionality implemented by BL31 is as follows.
544Architectural initialization
547Currently, BL31 performs a similar architectural initialization to BL1 as
548far as system register settings are concerned. Since BL1 code resides in ROM,
549architectural initialization in BL31 allows override of any previous
550initialization done by BL1.
552BL31 initializes the per-CPU data framework, which provides a cache of
553frequently accessed per-CPU data optimised for fast, concurrent manipulation
554on different CPUs. This buffer includes pointers to per-CPU contexts, crash
555buffer, CPU reset and power down operations, PSCI data, platform data and so on.
557It then replaces the exception vectors populated by BL1 with its own. BL31
558exception vectors implement more elaborate support for handling SMCs since this
559is the only mechanism to access the runtime services implemented by BL31 (PSCI
560for example). BL31 checks each SMC for validity as specified by the
Sandrine Bailleux71ac9312020-04-17 14:06:52 +0200561`SMC Calling Convention`_ before passing control to the required SMC
Douglas Raillard6f625742017-06-28 15:23:03 +0100562handler routine.
564BL31 programs the ``CNTFRQ_EL0`` register with the clock frequency of the system
565counter, which is provided by the platform.
567Platform initialization
570BL31 performs detailed platform initialization, which enables normal world
571software to function correctly.
Dan Handley4def07d2018-03-01 18:44:00 +0000573On Arm platforms, this consists of the following:
Douglas Raillard6f625742017-06-28 15:23:03 +0100574
575- Initialize the console.
576- Configure the Interconnect to enable hardware coherency.
577- Enable the MMU and map the memory it needs to access.
578- Initialize the generic interrupt controller.
579- Initialize the power controller device.
580- Detect the system topology.
582Runtime services initialization
585BL31 is responsible for initializing the runtime services. One of them is PSCI.
587As part of the PSCI initializations, BL31 detects the system topology. It also
588initializes the data structures that implement the state machine used to track
589the state of power domain nodes. The state can be one of ``OFF``, ``RUN`` or
590``RETENTION``. All secondary CPUs are initially in the ``OFF`` state. The cluster
591that the primary CPU belongs to is ``ON``; any other cluster is ``OFF``. It also
592initializes the locks that protect them. BL31 accesses the state of a CPU or
593cluster immediately after reset and before the data cache is enabled in the
594warm boot path. It is not currently possible to use 'exclusive' based spinlocks,
595therefore BL31 uses locks based on Lamport's Bakery algorithm instead.
597The runtime service framework and its initialization is described in more
598detail in the "EL3 runtime services framework" section below.
600Details about the status of the PSCI implementation are provided in the
601"Power State Coordination Interface" section below.
603AArch64 BL32 (Secure-EL1 Payload) image initialization
606If a BL32 image is present then there must be a matching Secure-EL1 Payload
607Dispatcher (SPD) service (see later for details). During initialization
608that service must register a function to carry out initialization of BL32
609once the runtime services are fully initialized. BL31 invokes such a
610registered function to initialize BL32 before running BL33. This initialization
611is not necessary for AArch32 SPs.
613Details on BL32 initialization and the SPD's role are described in the
Paul Beesley43f35ef2019-05-29 13:59:40 +0100614:ref:`firmware_design_sel1_spd` section below.
Douglas Raillard6f625742017-06-28 15:23:03 +0100615
616BL33 (Non-trusted Firmware) execution
619EL3 Runtime Software initializes the EL2 or EL1 processor context for normal-
620world cold boot, ensuring that no secure state information finds its way into
621the non-secure execution state. EL3 Runtime Software uses the entrypoint
622information provided by BL2 to jump to the Non-trusted firmware image (BL33)
623at the highest available Exception Level (EL2 if available, otherwise EL1).
625Using alternative Trusted Boot Firmware in place of BL1 & BL2 (AArch64 only)
628Some platforms have existing implementations of Trusted Boot Firmware that
Dan Handley4def07d2018-03-01 18:44:00 +0000629would like to use TF-A BL31 for the EL3 Runtime Software. To enable this
630firmware architecture it is important to provide a fully documented and stable
631interface between the Trusted Boot Firmware and BL31.
Douglas Raillard6f625742017-06-28 15:23:03 +0100632
633Future changes to the BL31 interface will be done in a backwards compatible
634way, and this enables these firmware components to be independently enhanced/
635updated to develop and exploit new functionality.
637Required CPU state when calling ``bl31_entrypoint()`` during cold boot
640This function must only be called by the primary CPU.
642On entry to this function the calling primary CPU must be executing in AArch64
643EL3, little-endian data access, and all interrupt sources masked:
647 PSTATE.EL = 3
648 PSTATE.RW = 1
649 PSTATE.DAIF = 0xf
650 SCTLR_EL3.EE = 0
652X0 and X1 can be used to pass information from the Trusted Boot Firmware to the
653platform code in BL31:
Dan Handley4def07d2018-03-01 18:44:00 +0000657 X0 : Reserved for common TF-A information
Douglas Raillard6f625742017-06-28 15:23:03 +0100658 X1 : Platform specific information
660BL31 zero-init sections (e.g. ``.bss``) should not contain valid data on entry,
661these will be zero filled prior to invoking platform setup code.
663Use of the X0 and X1 parameters
666The parameters are platform specific and passed from ``bl31_entrypoint()`` to
667``bl31_early_platform_setup()``. The value of these parameters is never directly
668used by the common BL31 code.
670The convention is that ``X0`` conveys information regarding the BL31, BL32 and
671BL33 images from the Trusted Boot firmware and ``X1`` can be used for other
Dan Handley4def07d2018-03-01 18:44:00 +0000672platform specific purpose. This convention allows platforms which use TF-A's
673BL1 and BL2 images to transfer additional platform specific information from
674Secure Boot without conflicting with future evolution of TF-A using ``X0`` to
675pass a ``bl31_params`` structure.
Douglas Raillard6f625742017-06-28 15:23:03 +0100676
677BL31 common and SPD initialization code depends on image and entrypoint
678information about BL33 and BL32, which is provided via BL31 platform APIs.
679This information is required until the start of execution of BL33. This
680information can be provided in a platform defined manner, e.g. compiled into
681the platform code in BL31, or provided in a platform defined memory location
682by the Trusted Boot firmware, or passed from the Trusted Boot Firmware via the
683Cold boot Initialization parameters. This data may need to be cleaned out of
684the CPU caches if it is provided by an earlier boot stage and then accessed by
685BL31 platform code before the caches are enabled.
Dan Handley4def07d2018-03-01 18:44:00 +0000687TF-A's BL2 implementation passes a ``bl31_params`` structure in
688``X0`` and the Arm development platforms interpret this in the BL31 platform
Douglas Raillard6f625742017-06-28 15:23:03 +0100689code.
691MMU, Data caches & Coherency
694BL31 does not depend on the enabled state of the MMU, data caches or
695interconnect coherency on entry to ``bl31_entrypoint()``. If these are disabled
696on entry, these should be enabled during ``bl31_plat_arch_setup()``.
698Data structures used in the BL31 cold boot interface
701These structures are designed to support compatibility and independent
702evolution of the structures and the firmware images. For example, a version of
703BL31 that can interpret the BL3x image information from different versions of
Sandrine Bailleuxf3cacad2019-02-08 15:26:36 +0100704BL2, a platform that uses an extended entry_point_info structure to convey
Douglas Raillard6f625742017-06-28 15:23:03 +0100705additional register information to BL31, or a ELF image loader that can convey
706more details about the firmware images.
708To support these scenarios the structures are versioned and sized, which enables
709BL31 to detect which information is present and respond appropriately. The
710``param_header`` is defined to capture this information:
712.. code:: c
714 typedef struct param_header {
715 uint8_t type; /* type of the structure */
716 uint8_t version; /* version of this structure */
717 uint16_t size; /* size of this structure in bytes */
718 uint32_t attr; /* attributes: unused bits SBZ */
719 } param_header_t;
721The structures using this format are ``entry_point_info``, ``image_info`` and
722``bl31_params``. The code that allocates and populates these structures must set
723the header fields appropriately, and the ``SET_PARAM_HEAD()`` a macro is defined
724to simplify this action.
726Required CPU state for BL31 Warm boot initialization
Dan Handley4def07d2018-03-01 18:44:00 +0000729When requesting a CPU power-on, or suspending a running CPU, TF-A provides
730the platform power management code with a Warm boot initialization
731entry-point, to be invoked by the CPU immediately after the reset handler.
732On entry to the Warm boot initialization function the calling CPU must be in
733AArch64 EL3, little-endian data access and all interrupt sources masked:
Douglas Raillard6f625742017-06-28 15:23:03 +0100734
737 PSTATE.EL = 3
738 PSTATE.RW = 1
739 PSTATE.DAIF = 0xf
740 SCTLR_EL3.EE = 0
742The PSCI implementation will initialize the processor state and ensure that the
743platform power management code is then invoked as required to initialize all
744necessary system, cluster and CPU resources.
746AArch32 EL3 Runtime Software entrypoint interface
749To enable this firmware architecture it is important to provide a fully
750documented and stable interface between the Trusted Boot Firmware and the
751AArch32 EL3 Runtime Software.
753Future changes to the entrypoint interface will be done in a backwards
754compatible way, and this enables these firmware components to be independently
755enhanced/updated to develop and exploit new functionality.
757Required CPU state when entering during cold boot
760This function must only be called by the primary CPU.
762On entry to this function the calling primary CPU must be executing in AArch32
763EL3, little-endian data access, and all interrupt sources masked:
767 PSTATE.AIF = 0x7
768 SCTLR.EE = 0
770R0 and R1 are used to pass information from the Trusted Boot Firmware to the
771platform code in AArch32 EL3 Runtime Software:
Dan Handley4def07d2018-03-01 18:44:00 +0000775 R0 : Reserved for common TF-A information
Douglas Raillard6f625742017-06-28 15:23:03 +0100776 R1 : Platform specific information
778Use of the R0 and R1 parameters
781The parameters are platform specific and the convention is that ``R0`` conveys
782information regarding the BL3x images from the Trusted Boot firmware and ``R1``
783can be used for other platform specific purpose. This convention allows
Dan Handley4def07d2018-03-01 18:44:00 +0000784platforms which use TF-A's BL1 and BL2 images to transfer additional platform
785specific information from Secure Boot without conflicting with future
786evolution of TF-A using ``R0`` to pass a ``bl_params`` structure.
Douglas Raillard6f625742017-06-28 15:23:03 +0100787
788The AArch32 EL3 Runtime Software is responsible for entry into BL33. This
789information can be obtained in a platform defined manner, e.g. compiled into
790the AArch32 EL3 Runtime Software, or provided in a platform defined memory
791location by the Trusted Boot firmware, or passed from the Trusted Boot Firmware
792via the Cold boot Initialization parameters. This data may need to be cleaned
793out of the CPU caches if it is provided by an earlier boot stage and then
794accessed by AArch32 EL3 Runtime Software before the caches are enabled.
Dan Handley4def07d2018-03-01 18:44:00 +0000796When using AArch32 EL3 Runtime Software, the Arm development platforms pass a
Douglas Raillard6f625742017-06-28 15:23:03 +0100797``bl_params`` structure in ``R0`` from BL2 to be interpreted by AArch32 EL3 Runtime
798Software platform code.
800MMU, Data caches & Coherency
803AArch32 EL3 Runtime Software must not depend on the enabled state of the MMU,
804data caches or interconnect coherency in its entrypoint. They must be explicitly
805enabled if required.
807Data structures used in cold boot interface
810The AArch32 EL3 Runtime Software cold boot interface uses ``bl_params`` instead
811of ``bl31_params``. The ``bl_params`` structure is based on the convention
812described in AArch64 BL31 cold boot interface section.
814Required CPU state for warm boot initialization
817When requesting a CPU power-on, or suspending a running CPU, AArch32 EL3
818Runtime Software must ensure execution of a warm boot initialization entrypoint.
Sandrine Bailleuxf3cacad2019-02-08 15:26:36 +0100819If TF-A BL1 is used and the PROGRAMMABLE_RESET_ADDRESS build flag is false,
Dan Handley4def07d2018-03-01 18:44:00 +0000820then AArch32 EL3 Runtime Software must ensure that BL1 branches to the warm
821boot entrypoint by arranging for the BL1 platform function,
Sandrine Bailleuxf3cacad2019-02-08 15:26:36 +0100822plat_get_my_entrypoint(), to return a non-zero value.
Douglas Raillard6f625742017-06-28 15:23:03 +0100823
824In this case, the warm boot entrypoint must be in AArch32 EL3, little-endian
825data access and all interrupt sources masked:
829 PSTATE.AIF = 0x7
830 SCTLR.EE = 0
Dan Handley4def07d2018-03-01 18:44:00 +0000832The warm boot entrypoint may be implemented by using TF-A
Douglas Raillard6f625742017-06-28 15:23:03 +0100833``psci_warmboot_entrypoint()`` function. In that case, the platform must fulfil
Paul Beesley34760952019-04-12 14:19:42 +0100834the pre-requisites mentioned in the
835:ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`.
Douglas Raillard6f625742017-06-28 15:23:03 +0100836
837EL3 runtime services framework
840Software executing in the non-secure state and in the secure state at exception
841levels lower than EL3 will request runtime services using the Secure Monitor
842Call (SMC) instruction. These requests will follow the convention described in
843the SMC Calling Convention PDD (`SMCCC`_). The `SMCCC`_ assigns function
844identifiers to each SMC request and describes how arguments are passed and
847The EL3 runtime services framework enables the development of services by
848different providers that can be easily integrated into final product firmware.
849The following sections describe the framework which facilitates the
850registration, initialization and use of runtime services in EL3 Runtime
851Software (BL31).
853The design of the runtime services depends heavily on the concepts and
854definitions described in the `SMCCC`_, in particular SMC Function IDs, Owning
855Entity Numbers (OEN), Fast and Yielding calls, and the SMC32 and SMC64 calling
856conventions. Please refer to that document for more detailed explanation of
857these terms.
859The following runtime services are expected to be implemented first. They have
860not all been instantiated in the current implementation.
862#. Standard service calls
864 This service is for management of the entire system. The Power State
865 Coordination Interface (`PSCI`_) is the first set of standard service calls
Dan Handley4def07d2018-03-01 18:44:00 +0000866 defined by Arm (see PSCI section later).
Douglas Raillard6f625742017-06-28 15:23:03 +0100867
868#. Secure-EL1 Payload Dispatcher service
870 If a system runs a Trusted OS or other Secure-EL1 Payload (SP) then
871 it also requires a *Secure Monitor* at EL3 to switch the EL1 processor
872 context between the normal world (EL1/EL2) and trusted world (Secure-EL1).
873 The Secure Monitor will make these world switches in response to SMCs. The
874 `SMCCC`_ provides for such SMCs with the Trusted OS Call and Trusted
875 Application Call OEN ranges.
877 The interface between the EL3 Runtime Software and the Secure-EL1 Payload is
878 not defined by the `SMCCC`_ or any other standard. As a result, each
879 Secure-EL1 Payload requires a specific Secure Monitor that runs as a runtime
Dan Handley4def07d2018-03-01 18:44:00 +0000880 service - within TF-A this service is referred to as the Secure-EL1 Payload
881 Dispatcher (SPD).
Douglas Raillard6f625742017-06-28 15:23:03 +0100882
Dan Handley4def07d2018-03-01 18:44:00 +0000883 TF-A provides a Test Secure-EL1 Payload (TSP) and its associated Dispatcher
884 (TSPD). Details of SPD design and TSP/TSPD operation are described in the
Paul Beesley43f35ef2019-05-29 13:59:40 +0100885 :ref:`firmware_design_sel1_spd` section below.
Douglas Raillard6f625742017-06-28 15:23:03 +0100886
887#. CPU implementation service
889 This service will provide an interface to CPU implementation specific
890 services for a given platform e.g. access to processor errata workarounds.
891 This service is currently unimplemented.
Dan Handley4def07d2018-03-01 18:44:00 +0000893Additional services for Arm Architecture, SiP and OEM calls can be implemented.
Douglas Raillard6f625742017-06-28 15:23:03 +0100894Each implemented service handles a range of SMC function identifiers as
895described in the `SMCCC`_.
900A runtime service is registered using the ``DECLARE_RT_SVC()`` macro, specifying
901the name of the service, the range of OENs covered, the type of service and
902initialization and call handler functions. This macro instantiates a ``const struct rt_svc_desc`` for the service with these details (see ``runtime_svc.h``).
903This structure is allocated in a special ELF section ``rt_svc_descs``, enabling
904the framework to find all service descriptors included into BL31.
906The specific service for a SMC Function is selected based on the OEN and call
907type of the Function ID, and the framework uses that information in the service
908descriptor to identify the handler for the SMC Call.
910The service descriptors do not include information to identify the precise set
911of SMC function identifiers supported by this service implementation, the
912security state from which such calls are valid nor the capability to support
91364-bit and/or 32-bit callers (using SMC32 or SMC64). Responding appropriately
914to these aspects of a SMC call is the responsibility of the service
915implementation, the framework is focused on integration of services from
916different providers and minimizing the time taken by the framework before the
917service handler is invoked.
919Details of the parameters, requirements and behavior of the initialization and
920call handling functions are provided in the following sections.
925``runtime_svc_init()`` in ``runtime_svc.c`` initializes the runtime services
926framework running on the primary CPU during cold boot as part of the BL31
927initialization. This happens prior to initializing a Trusted OS and running
928Normal world boot firmware that might in turn use these services.
929Initialization involves validating each of the declared runtime service
930descriptors, calling the service initialization function and populating the
931index used for runtime lookup of the service.
933The BL31 linker script collects all of the declared service descriptors into a
934single array and defines symbols that allow the framework to locate and traverse
935the array, and determine its size.
937The framework does basic validation of each descriptor to halt firmware
938initialization if service declaration errors are detected. The framework does
939not check descriptors for the following error conditions, and may behave in an
940unpredictable manner under such scenarios:
942#. Overlapping OEN ranges
943#. Multiple descriptors for the same range of OENs and ``call_type``
944#. Incorrect range of owning entity numbers for a given ``call_type``
946Once validated, the service ``init()`` callback is invoked. This function carries
947out any essential EL3 initialization before servicing requests. The ``init()``
948function is only invoked on the primary CPU during cold boot. If the service
949uses per-CPU data this must either be initialized for all CPUs during this call,
950or be done lazily when a CPU first issues an SMC call to that service. If
951``init()`` returns anything other than ``0``, this is treated as an initialization
952error and the service is ignored: this does not cause the firmware to halt.
954The OEN and call type fields present in the SMC Function ID cover a total of
955128 distinct services, but in practice a single descriptor can cover a range of
956OENs, e.g. SMCs to call a Trusted OS function. To optimize the lookup of a
957service handler, the framework uses an array of 128 indices that map every
958distinct OEN/call-type combination either to one of the declared services or to
959indicate the service is not handled. This ``rt_svc_descs_indices[]`` array is
960populated for all of the OENs covered by a service after the service ``init()``
961function has reported success. So a service that fails to initialize will never
962have it's ``handle()`` function invoked.
964The following figure shows how the ``rt_svc_descs_indices[]`` index maps the SMC
965Function ID call type and OEN onto a specific service handler in the
966``rt_svc_descs[]`` array.
968|Image 1|
Madhukar Pappireddy6844c342020-07-29 09:37:25 -0500970.. _handling-an-smc:
Douglas Raillard6f625742017-06-28 15:23:03 +0100972Handling an SMC
975When the EL3 runtime services framework receives a Secure Monitor Call, the SMC
976Function ID is passed in W0 from the lower exception level (as per the
977`SMCCC`_). If the calling register width is AArch32, it is invalid to invoke an
978SMC Function which indicates the SMC64 calling convention: such calls are
979ignored and return the Unknown SMC Function Identifier result code ``0xFFFFFFFF``
980in R0/X0.
982Bit[31] (fast/yielding call) and bits[29:24] (owning entity number) of the SMC
983Function ID are combined to index into the ``rt_svc_descs_indices[]`` array. The
984resulting value might indicate a service that has no handler, in this case the
985framework will also report an Unknown SMC Function ID. Otherwise, the value is
986used as a further index into the ``rt_svc_descs[]`` array to locate the required
987service and handler.
989The service's ``handle()`` callback is provided with five of the SMC parameters
990directly, the others are saved into memory for retrieval (if needed) by the
991handler. The handler is also provided with an opaque ``handle`` for use with the
992supporting library for parameter retrieval, setting return values and context
Olivier Deprez0fe7b9f2022-10-11 15:38:27 +0200993manipulation. The ``flags`` parameter indicates the security state of the caller
994and the state of the SVE hint bit per the SMCCCv1.3. The framework finally sets
995up the execution stack for the handler, and invokes the services ``handle()``
Douglas Raillard6f625742017-06-28 15:23:03 +0100997
Madhukar Pappireddye34cc0c2019-11-09 23:28:08 -0600998On return from the handler the result registers are populated in X0-X7 as needed
999before restoring the stack and CPU state and returning from the original SMC.
Douglas Raillard6f625742017-06-28 15:23:03 +01001000
Jeenu Viswambharane31d76f2017-10-18 14:30:53 +01001001Exception Handling Framework
johpow01526f2bd2020-07-28 13:07:25 -05001004Please refer to the :ref:`Exception Handling Framework` document.
Jeenu Viswambharane31d76f2017-10-18 14:30:53 +01001005
Douglas Raillard6f625742017-06-28 15:23:03 +01001006Power State Coordination Interface
1009TODO: Provide design walkthrough of PSCI implementation.
Roberto Vargasfe3e40e2017-09-12 10:28:35 +01001011The PSCI v1.1 specification categorizes APIs as optional and mandatory. All the
1012mandatory APIs in PSCI v1.1, PSCI v1.0 and in PSCI v0.2 draft specification
Douglas Raillard6f625742017-06-28 15:23:03 +01001013`Power State Coordination Interface PDD`_ are implemented. The table lists
Roberto Vargasfe3e40e2017-09-12 10:28:35 +01001014the PSCI v1.1 APIs and their support in generic code.
Douglas Raillard6f625742017-06-28 15:23:03 +01001015
Sandrine Bailleuxf3cacad2019-02-08 15:26:36 +01001016An API implementation might have a dependency on platform code e.g. CPU_SUSPEND
Douglas Raillard6f625742017-06-28 15:23:03 +01001017requires the platform to export a part of the implementation. Hence the level
1018of support of the mandatory APIs depends upon the support exported by the
1019platform port as well. The Juno and FVP (all variants) platforms export all the
1020required support.
Roberto Vargasfe3e40e2017-09-12 10:28:35 +01001023| PSCI v1.1 API | Supported | Comments |
Douglas Raillard6f625742017-06-28 15:23:03 +01001024+=============================+=============+===============================+
Roberto Vargasfe3e40e2017-09-12 10:28:35 +01001025| ``PSCI_VERSION`` | Yes | The version returned is 1.1 |
Douglas Raillard6f625742017-06-28 15:23:03 +01001026+-----------------------------+-------------+-------------------------------+
1027| ``CPU_SUSPEND`` | Yes\* | |
1029| ``CPU_OFF`` | Yes\* | |
1031| ``CPU_ON`` | Yes\* | |
1033| ``AFFINITY_INFO`` | Yes | |
1035| ``MIGRATE`` | Yes\*\* | |
1037| ``MIGRATE_INFO_TYPE`` | Yes\*\* | |
1039| ``MIGRATE_INFO_CPU`` | Yes\*\* | |
1041| ``SYSTEM_OFF`` | Yes\* | |
1043| ``SYSTEM_RESET`` | Yes\* | |
1045| ``PSCI_FEATURES`` | Yes | |
1047| ``CPU_FREEZE`` | No | |
1049| ``CPU_DEFAULT_SUSPEND`` | No | |
1051| ``NODE_HW_STATE`` | Yes\* | |
1053| ``SYSTEM_SUSPEND`` | Yes\* | |
1055| ``PSCI_SET_SUSPEND_MODE`` | No | |
1057| ``PSCI_STAT_RESIDENCY`` | Yes\* | |
1059| ``PSCI_STAT_COUNT`` | Yes\* | |
Roberto Vargasfe3e40e2017-09-12 10:28:35 +01001061| ``SYSTEM_RESET2`` | Yes\* | |
1063| ``MEM_PROTECT`` | Yes\* | |
1065| ``MEM_PROTECT_CHECK_RANGE`` | Yes\* | |
Douglas Raillard6f625742017-06-28 15:23:03 +01001067
1068\*Note : These PSCI APIs require platform power management hooks to be
1069registered with the generic PSCI code to be supported.
1071\*\*Note : These PSCI APIs require appropriate Secure Payload Dispatcher
1072hooks to be registered with the generic PSCI code to be supported.
Dan Handley4def07d2018-03-01 18:44:00 +00001074The PSCI implementation in TF-A is a library which can be integrated with
1075AArch64 or AArch32 EL3 Runtime Software for Armv8-A systems. A guide to
1076integrating PSCI library with AArch32 EL3 Runtime Software can be found
Paul Beesley34760952019-04-12 14:19:42 +01001077at :ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`.
1079.. _firmware_design_sel1_spd:
Douglas Raillard6f625742017-06-28 15:23:03 +01001080
1081Secure-EL1 Payloads and Dispatchers
1084On a production system that includes a Trusted OS running in Secure-EL1/EL0,
1085the Trusted OS is coupled with a companion runtime service in the BL31
1086firmware. This service is responsible for the initialisation of the Trusted
1087OS and all communications with it. The Trusted OS is the BL32 stage of the
Dan Handley4def07d2018-03-01 18:44:00 +00001088boot flow in TF-A. The firmware will attempt to locate, load and execute a
1089BL32 image.
Douglas Raillard6f625742017-06-28 15:23:03 +01001090
Dan Handley4def07d2018-03-01 18:44:00 +00001091TF-A uses a more general term for the BL32 software that runs at Secure-EL1 -
1092the *Secure-EL1 Payload* - as it is not always a Trusted OS.
Douglas Raillard6f625742017-06-28 15:23:03 +01001093
Dan Handley4def07d2018-03-01 18:44:00 +00001094TF-A provides a Test Secure-EL1 Payload (TSP) and a Test Secure-EL1 Payload
1095Dispatcher (TSPD) service as an example of how a Trusted OS is supported on a
1096production system using the Runtime Services Framework. On such a system, the
1097Test BL32 image and service are replaced by the Trusted OS and its dispatcher
1098service. The TF-A build system expects that the dispatcher will define the
1099build flag ``NEED_BL32`` to enable it to include the BL32 in the build either
1100as a binary or to compile from source depending on whether the ``BL32`` build
1101option is specified or not.
Douglas Raillard6f625742017-06-28 15:23:03 +01001102
1103The TSP runs in Secure-EL1. It is designed to demonstrate synchronous
1104communication with the normal-world software running in EL1/EL2. Communication
1105is initiated by the normal-world software
1107- either directly through a Fast SMC (as defined in the `SMCCC`_)
1109- or indirectly through a `PSCI`_ SMC. The `PSCI`_ implementation in turn
1110 informs the TSPD about the requested power management operation. This allows
1111 the TSP to prepare for or respond to the power state change
1113The TSPD service is responsible for.
1115- Initializing the TSP
1117- Routing requests and responses between the secure and the non-secure
1118 states during the two types of communications just described
1120Initializing a BL32 Image
1123The Secure-EL1 Payload Dispatcher (SPD) service is responsible for initializing
1124the BL32 image. It needs access to the information passed by BL2 to BL31 to do
1125so. This is provided by:
1127.. code:: c
1129 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t);
1131which returns a reference to the ``entry_point_info`` structure corresponding to
1132the image which will be run in the specified security state. The SPD uses this
1133API to get entry point information for the SECURE image, BL32.
1135In the absence of a BL32 image, BL31 passes control to the normal world
1136bootloader image (BL33). When the BL32 image is present, it is typical
1137that the SPD wants control to be passed to BL32 first and then later to BL33.
1139To do this the SPD has to register a BL32 initialization function during
1140initialization of the SPD service. The BL32 initialization function has this
1143.. code:: c
1145 int32_t init(void);
1147and is registered using the ``bl31_register_bl32_init()`` function.
Dan Handley4def07d2018-03-01 18:44:00 +00001149TF-A supports two approaches for the SPD to pass control to BL32 before
1150returning through EL3 and running the non-trusted firmware (BL33):
Douglas Raillard6f625742017-06-28 15:23:03 +01001151
1152#. In the BL32 setup function, use ``bl31_set_next_image_type()`` to
1153 request that the exit from ``bl31_main()`` is to the BL32 entrypoint in
1154 Secure-EL1. BL31 will exit to BL32 using the asynchronous method by
1155 calling ``bl31_prepare_next_image_entry()`` and ``el3_exit()``.
1157 When the BL32 has completed initialization at Secure-EL1, it returns to
1158 BL31 by issuing an SMC, using a Function ID allocated to the SPD. On
1159 receipt of this SMC, the SPD service handler should switch the CPU context
1160 from trusted to normal world and use the ``bl31_set_next_image_type()`` and
1161 ``bl31_prepare_next_image_entry()`` functions to set up the initial return to
1162 the normal world firmware BL33. On return from the handler the framework
1163 will exit to EL2 and run BL33.
1165#. The BL32 setup function registers an initialization function using
1166 ``bl31_register_bl32_init()`` which provides a SPD-defined mechanism to
1167 invoke a 'world-switch synchronous call' to Secure-EL1 to run the BL32
1168 entrypoint.
Paul Beesleye1c50262019-03-13 16:20:44 +00001169
1170 .. note::
1171 The Test SPD service included with TF-A provides one implementation
1172 of such a mechanism.
Douglas Raillard6f625742017-06-28 15:23:03 +01001173
1174 On completion BL32 returns control to BL31 via a SMC, and on receipt the
1175 SPD service handler invokes the synchronous call return mechanism to return
1176 to the BL32 initialization function. On return from this function,
1177 ``bl31_main()`` will set up the return to the normal world firmware BL33 and
1178 continue the boot process in the normal world.
Jeenu Viswambharan579b4ad2017-08-24 15:43:44 +01001180Crash Reporting in BL31
Douglas Raillard6f625742017-06-28 15:23:03 +01001182
1183BL31 implements a scheme for reporting the processor state when an unhandled
1184exception is encountered. The reporting mechanism attempts to preserve all the
1185register contents and report it via a dedicated UART (PL011 console). BL31
1186reports the general purpose, EL3, Secure EL1 and some EL2 state registers.
1188A dedicated per-CPU crash stack is maintained by BL31 and this is retrieved via
1189the per-CPU pointer cache. The implementation attempts to minimise the memory
1190required for this feature. The file ``crash_reporting.S`` contains the
1191implementation for crash reporting.
1193The sample crash output is shown below.
Alexei Fedorovb4292bc2020-03-03 13:31:58 +00001197 x0 = 0x000000002a4a0000
1198 x1 = 0x0000000000000001
1199 x2 = 0x0000000000000002
1200 x3 = 0x0000000000000003
1201 x4 = 0x0000000000000004
1202 x5 = 0x0000000000000005
1203 x6 = 0x0000000000000006
1204 x7 = 0x0000000000000007
1205 x8 = 0x0000000000000008
1206 x9 = 0x0000000000000009
1207 x10 = 0x0000000000000010
1208 x11 = 0x0000000000000011
1209 x12 = 0x0000000000000012
1210 x13 = 0x0000000000000013
1211 x14 = 0x0000000000000014
1212 x15 = 0x0000000000000015
1213 x16 = 0x0000000000000016
1214 x17 = 0x0000000000000017
1215 x18 = 0x0000000000000018
1216 x19 = 0x0000000000000019
1217 x20 = 0x0000000000000020
1218 x21 = 0x0000000000000021
1219 x22 = 0x0000000000000022
1220 x23 = 0x0000000000000023
1221 x24 = 0x0000000000000024
1222 x25 = 0x0000000000000025
1223 x26 = 0x0000000000000026
1224 x27 = 0x0000000000000027
1225 x28 = 0x0000000000000028
1226 x29 = 0x0000000000000029
1227 x30 = 0x0000000088000b78
1228 scr_el3 = 0x000000000003073d
1229 sctlr_el3 = 0x00000000b0cd183f
1230 cptr_el3 = 0x0000000000000000
1231 tcr_el3 = 0x000000008080351c
1232 daif = 0x00000000000002c0
1233 mair_el3 = 0x00000000004404ff
1234 spsr_el3 = 0x0000000060000349
1235 elr_el3 = 0x0000000088000114
1236 ttbr0_el3 = 0x0000000004018201
1237 esr_el3 = 0x00000000be000000
1238 far_el3 = 0x0000000000000000
1239 spsr_el1 = 0x0000000000000000
1240 elr_el1 = 0x0000000000000000
1241 spsr_abt = 0x0000000000000000
1242 spsr_und = 0x0000000000000000
1243 spsr_irq = 0x0000000000000000
1244 spsr_fiq = 0x0000000000000000
1245 sctlr_el1 = 0x0000000030d00800
1246 actlr_el1 = 0x0000000000000000
1247 cpacr_el1 = 0x0000000000000000
1248 csselr_el1 = 0x0000000000000000
1249 sp_el1 = 0x0000000000000000
1250 esr_el1 = 0x0000000000000000
1251 ttbr0_el1 = 0x0000000000000000
1252 ttbr1_el1 = 0x0000000000000000
1253 mair_el1 = 0x0000000000000000
1254 amair_el1 = 0x0000000000000000
1255 tcr_el1 = 0x0000000000000000
1256 tpidr_el1 = 0x0000000000000000
1257 tpidr_el0 = 0x0000000000000000
1258 tpidrro_el0 = 0x0000000000000000
1259 par_el1 = 0x0000000000000000
1260 mpidr_el1 = 0x0000000080000000
1261 afsr0_el1 = 0x0000000000000000
1262 afsr1_el1 = 0x0000000000000000
1263 contextidr_el1 = 0x0000000000000000
1264 vbar_el1 = 0x0000000000000000
1265 cntp_ctl_el0 = 0x0000000000000000
1266 cntp_cval_el0 = 0x0000000000000000
1267 cntv_ctl_el0 = 0x0000000000000000
1268 cntv_cval_el0 = 0x0000000000000000
1269 cntkctl_el1 = 0x0000000000000000
1270 sp_el0 = 0x0000000004014940
1271 isr_el1 = 0x0000000000000000
1272 dacr32_el2 = 0x0000000000000000
1273 ifsr32_el2 = 0x0000000000000000
1274 icc_hppir0_el1 = 0x00000000000003ff
1275 icc_hppir1_el1 = 0x00000000000003ff
1276 icc_ctlr_el3 = 0x0000000000080400
1277 gicd_ispendr regs (Offsets 0x200-0x278)
1278 Offset Value
1279 0x200: 0x0000000000000000
1280 0x208: 0x0000000000000000
1281 0x210: 0x0000000000000000
1282 0x218: 0x0000000000000000
1283 0x220: 0x0000000000000000
1284 0x228: 0x0000000000000000
1285 0x230: 0x0000000000000000
1286 0x238: 0x0000000000000000
1287 0x240: 0x0000000000000000
1288 0x248: 0x0000000000000000
1289 0x250: 0x0000000000000000
1290 0x258: 0x0000000000000000
1291 0x260: 0x0000000000000000
1292 0x268: 0x0000000000000000
1293 0x270: 0x0000000000000000
1294 0x278: 0x0000000000000000
Douglas Raillard6f625742017-06-28 15:23:03 +01001295
1296Guidelines for Reset Handlers
Dan Handley4def07d2018-03-01 18:44:00 +00001299TF-A implements a framework that allows CPU and platform ports to perform
1300actions very early after a CPU is released from reset in both the cold and warm
1301boot paths. This is done by calling the ``reset_handler()`` function in both
1302the BL1 and BL31 images. It in turn calls the platform and CPU specific reset
1303handling functions.
Douglas Raillard6f625742017-06-28 15:23:03 +01001304
1305Details for implementing a CPU specific reset handler can be found in
1306Section 8. Details for implementing a platform specific reset handler can be
Paul Beesley34760952019-04-12 14:19:42 +01001307found in the :ref:`Porting Guide` (see the ``plat_reset_handler()`` function).
Douglas Raillard6f625742017-06-28 15:23:03 +01001308
1309When adding functionality to a reset handler, keep in mind that if a different
1310reset handling behavior is required between the first and the subsequent
1311invocations of the reset handling code, this should be detected at runtime.
1312In other words, the reset handler should be able to detect whether an action has
1313already been performed and act as appropriate. Possible courses of actions are,
1314e.g. skip the action the second time, or undo/redo it.
Madhukar Pappireddy6844c342020-07-29 09:37:25 -05001316.. _configuring-secure-interrupts:
Jeenu Viswambharanc639e8e2017-09-22 08:32:09 +01001318Configuring secure interrupts
1321The GIC driver is responsible for performing initial configuration of secure
1322interrupts on the platform. To this end, the platform is expected to provide the
1323GIC driver (either GICv2 or GICv3, as selected by the platform) with the
1324interrupt configuration during the driver initialisation.
Antonio Nino Diazf9ed3cb2018-09-24 17:23:24 +01001326Secure interrupt configuration are specified in an array of secure interrupt
1327properties. In this scheme, in both GICv2 and GICv3 driver data structures, the
1328``interrupt_props`` member points to an array of interrupt properties. Each
Antonio Nino Diaz73308612019-02-28 13:35:21 +00001329element of the array specifies the interrupt number and its attributes
1330(priority, group, configuration). Each element of the array shall be populated
1331by the macro ``INTR_PROP_DESC()``. The macro takes the following arguments:
Jeenu Viswambharanc639e8e2017-09-22 08:32:09 +01001332
Antonio Nino Diazf9ed3cb2018-09-24 17:23:24 +01001333- 10-bit interrupt number,
Jeenu Viswambharanc639e8e2017-09-22 08:32:09 +01001334
Antonio Nino Diazf9ed3cb2018-09-24 17:23:24 +01001335- 8-bit interrupt priority,
Jeenu Viswambharanc639e8e2017-09-22 08:32:09 +01001336
Antonio Nino Diazf9ed3cb2018-09-24 17:23:24 +01001337- Interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1``,
1338 ``INTR_TYPE_NS``),
Jeenu Viswambharanc639e8e2017-09-22 08:32:09 +01001339
Antonio Nino Diazf9ed3cb2018-09-24 17:23:24 +01001340- Interrupt configuration (either ``GIC_INTR_CFG_LEVEL`` or
1341 ``GIC_INTR_CFG_EDGE``).
Jeenu Viswambharanc639e8e2017-09-22 08:32:09 +01001342
Paul Beesley34760952019-04-12 14:19:42 +01001343.. _firmware_design_cpu_ops_fwk:
Douglas Raillard6f625742017-06-28 15:23:03 +01001345CPU specific operations framework
Dan Handley4def07d2018-03-01 18:44:00 +00001348Certain aspects of the Armv8-A architecture are implementation defined,
1349that is, certain behaviours are not architecturally defined, but must be
1350defined and documented by individual processor implementations. TF-A
1351implements a framework which categorises the common implementation defined
1352behaviours and allows a processor to export its implementation of that
Douglas Raillard6f625742017-06-28 15:23:03 +01001353behaviour. The categories are:
1355#. Processor specific reset sequence.
1357#. Processor specific power down sequences.
1359#. Processor specific register dumping as a part of crash reporting.
1361#. Errata status reporting.
1363Each of the above categories fulfils a different requirement.
1365#. allows any processor specific initialization before the caches and MMU
1366 are turned on, like implementation of errata workarounds, entry into
1367 the intra-cluster coherency domain etc.
1369#. allows each processor to implement the power down sequence mandated in
1370 its Technical Reference Manual (TRM).
1372#. allows a processor to provide additional information to the developer
1373 in the event of a crash, for example Cortex-A53 has registers which
1374 can expose the data cache contents.
1376#. allows a processor to define a function that inspects and reports the status
1377 of all errata workarounds on that processor.
1379Please note that only 2. is mandated by the TRM.
1381The CPU specific operations framework scales to accommodate a large number of
1382different CPUs during power down and reset handling. The platform can specify
1383any CPU optimization it wants to enable for each CPU. It can also specify
1384the CPU errata workarounds to be applied for each CPU type during reset
1385handling by defining CPU errata compile time macros. Details on these macros
Paul Beesley34760952019-04-12 14:19:42 +01001386can be found in the :ref:`Arm CPU Specific Build Macros` document.
Douglas Raillard6f625742017-06-28 15:23:03 +01001387
1388The CPU specific operations framework depends on the ``cpu_ops`` structure which
1389needs to be exported for each type of CPU in the platform. It is defined in
1390``include/lib/cpus/aarch64/cpu_macros.S`` and has the following fields : ``midr``,
1391``reset_func()``, ``cpu_pwr_down_ops`` (array of power down functions) and
1394The CPU specific files in ``lib/cpus`` export a ``cpu_ops`` data structure with
1395suitable handlers for that CPU. For example, ``lib/cpus/aarch64/cortex_a53.S``
1396exports the ``cpu_ops`` for Cortex-A53 CPU. According to the platform
1397configuration, these CPU specific files must be included in the build by
1398the platform makefile. The generic CPU specific operations framework code exists
1399in ``lib/cpus/aarch64/cpu_helpers.S``.
1401CPU specific Reset Handling
1404After a reset, the state of the CPU when it calls generic reset handler is:
1405MMU turned off, both instruction and data caches turned off and not part
1406of any coherency domain.
1408The BL entrypoint code first invokes the ``plat_reset_handler()`` to allow
1409the platform to perform any system initialization required and any system
1410errata workarounds that needs to be applied. The ``get_cpu_ops_ptr()`` reads
1411the current CPU midr, finds the matching ``cpu_ops`` entry in the ``cpu_ops``
1412array and returns it. Note that only the part number and implementer fields
1413in midr are used to find the matching ``cpu_ops`` entry. The ``reset_func()`` in
1414the returned ``cpu_ops`` is then invoked which executes the required reset
1415handling for that CPU and also any errata workarounds enabled by the platform.
1416This function must preserve the values of general purpose registers x20 to x29.
1418Refer to Section "Guidelines for Reset Handlers" for general guidelines
1419regarding placement of code in a reset handler.
1421CPU specific power down sequence
1424During the BL31 initialization sequence, the pointer to the matching ``cpu_ops``
1425entry is stored in per-CPU data by ``init_cpu_ops()`` so that it can be quickly
1426retrieved during power down sequences.
1428Various CPU drivers register handlers to perform power down at certain power
1429levels for that specific CPU. The PSCI service, upon receiving a power down
1430request, determines the highest power level at which to execute power down
1431sequence for a particular CPU. It uses the ``prepare_cpu_pwr_dwn()`` function to
1432pick the right power down handler for the requested level. The function
1433retrieves ``cpu_ops`` pointer member of per-CPU data, and from that, further
1434retrieves ``cpu_pwr_down_ops`` array, and indexes into the required level. If the
1435requested power level is higher than what a CPU driver supports, the handler
1436registered for highest level is invoked.
1438At runtime the platform hooks for power down are invoked by the PSCI service to
1439perform platform specific operations during a power down sequence, for example
1440turning off CCI coherency during a cluster power down.
1442CPU specific register reporting during crash
1445If the crash reporting is enabled in BL31, when a crash occurs, the crash
1446reporting framework calls ``do_cpu_reg_dump`` which retrieves the matching
1447``cpu_ops`` using ``get_cpu_ops_ptr()`` function. The ``cpu_reg_dump()`` in
1448``cpu_ops`` is invoked, which then returns the CPU specific register values to
1449be reported and a pointer to the ASCII list of register names in a format
1450expected by the crash reporting framework.
Paul Beesley34760952019-04-12 14:19:42 +01001452.. _firmware_design_cpu_errata_reporting:
Douglas Raillard6f625742017-06-28 15:23:03 +01001454CPU errata status reporting
Dan Handley4def07d2018-03-01 18:44:00 +00001457Errata workarounds for CPUs supported in TF-A are applied during both cold and
1458warm boots, shortly after reset. Individual Errata workarounds are enabled as
1459build options. Some errata workarounds have potential run-time implications;
1460therefore some are enabled by default, others not. Platform ports shall
1461override build options to enable or disable errata as appropriate. The CPU
Douglas Raillard6f625742017-06-28 15:23:03 +01001462drivers take care of applying errata workarounds that are enabled and applicable
Paul Beesley34760952019-04-12 14:19:42 +01001463to a given CPU. Refer to :ref:`arm_cpu_macros_errata_workarounds` for more
Douglas Raillard6f625742017-06-28 15:23:03 +01001465
1466Functions in CPU drivers that apply errata workaround must follow the
1467conventions listed below.
1469The errata workaround must be authored as two separate functions:
1471- One that checks for errata. This function must determine whether that errata
1472 applies to the current CPU. Typically this involves matching the current
1473 CPUs revision and variant against a value that's known to be affected by the
1474 errata. If the function determines that the errata applies to this CPU, it
1475 must return ``ERRATA_APPLIES``; otherwise, it must return
1476 ``ERRATA_NOT_APPLIES``. The utility functions ``cpu_get_rev_var`` and
1477 ``cpu_rev_var_ls`` functions may come in handy for this purpose.
1479For an errata identified as ``E``, the check function must be named
1482This function will be invoked at different times, both from assembly and from
1483C run time. Therefore it must follow AAPCS, and must not use stack.
1485- Another one that applies the errata workaround. This function would call the
1486 check function described above, and applies errata workaround if required.
1488CPU drivers that apply errata workaround can optionally implement an assembly
1489function that report the status of errata workarounds pertaining to that CPU.
Antonio Nino Diaz73308612019-02-28 13:35:21 +00001490For a driver that registers the CPU, for example, ``cpux`` via ``declare_cpu_ops``
Douglas Raillard6f625742017-06-28 15:23:03 +01001491macro, the errata reporting function, if it exists, must be named
1492``cpux_errata_report``. This function will always be called with MMU enabled; it
1493must follow AAPCS and may use stack.
Dan Handley4def07d2018-03-01 18:44:00 +00001495In a debug build of TF-A, on a CPU that comes out of reset, both BL1 and the
1496runtime firmware (BL31 in AArch64, and BL32 in AArch32) will invoke errata
1497status reporting function, if one exists, for that type of CPU.
Douglas Raillard6f625742017-06-28 15:23:03 +01001498
1499To report the status of each errata workaround, the function shall use the
1500assembler macro ``report_errata``, passing it:
1502- The build option that enables the errata;
1504- The name of the CPU: this must be the same identifier that CPU driver
1505 registered itself with, using ``declare_cpu_ops``;
1507- And the errata identifier: the identifier must match what's used in the
1508 errata's check function described above.
1510The errata status reporting function will be called once per CPU type/errata
1511combination during the software's active life time.
Dan Handley4def07d2018-03-01 18:44:00 +00001513It's expected that whenever an errata workaround is submitted to TF-A, the
1514errata reporting function is appropriately extended to report its status as
Douglas Raillard6f625742017-06-28 15:23:03 +01001516
1517Reporting the status of errata workaround is for informational purpose only; it
1518has no functional significance.
1520Memory layout of BL images
1523Each bootloader image can be divided in 2 parts:
1525- the static contents of the image. These are data actually stored in the
1526 binary on the disk. In the ELF terminology, they are called ``PROGBITS``
1527 sections;
1529- the run-time contents of the image. These are data that don't occupy any
1530 space in the binary on the disk. The ELF binary just contains some
1531 metadata indicating where these data will be stored at run-time and the
1532 corresponding sections need to be allocated and initialized at run-time.
1533 In the ELF terminology, they are called ``NOBITS`` sections.
1535All PROGBITS sections are grouped together at the beginning of the image,
Dan Handley4def07d2018-03-01 18:44:00 +00001536followed by all NOBITS sections. This is true for all TF-A images and it is
1537governed by the linker scripts. This ensures that the raw binary images are
1538as small as possible. If a NOBITS section was inserted in between PROGBITS
1539sections then the resulting binary file would contain zero bytes in place of
1540this NOBITS section, making the image unnecessarily bigger. Smaller images
1541allow faster loading from the FIP to the main memory.
Douglas Raillard6f625742017-06-28 15:23:03 +01001542
Samuel Hollandf8578e62018-10-17 21:40:18 -05001543For BL31, a platform can specify an alternate location for NOBITS sections
1544(other than immediately following PROGBITS sections) by setting
1545``SEPARATE_NOBITS_REGION`` to 1 and defining ``BL31_NOBITS_BASE`` and
Douglas Raillard6f625742017-06-28 15:23:03 +01001548Linker scripts and symbols
1551Each bootloader stage image layout is described by its own linker script. The
1552linker scripts export some symbols into the program symbol table. Their values
Dan Handley4def07d2018-03-01 18:44:00 +00001553correspond to particular addresses. TF-A code can refer to these symbols to
1554figure out the image memory layout.
Douglas Raillard6f625742017-06-28 15:23:03 +01001555
Dan Handley4def07d2018-03-01 18:44:00 +00001556Linker symbols follow the following naming convention in TF-A.
Douglas Raillard6f625742017-06-28 15:23:03 +01001557
1558- ``__<SECTION>_START__``
1560 Start address of a given section named ``<SECTION>``.
1562- ``__<SECTION>_END__``
1564 End address of a given section named ``<SECTION>``. If there is an alignment
1565 constraint on the section's end address then ``__<SECTION>_END__`` corresponds
1566 to the end address of the section's actual contents, rounded up to the right
1567 boundary. Refer to the value of ``__<SECTION>_UNALIGNED_END__`` to know the
1568 actual end address of the section's contents.
1572 End address of a given section named ``<SECTION>`` without any padding or
1573 rounding up due to some alignment constraint.
1575- ``__<SECTION>_SIZE__``
1577 Size (in bytes) of a given section named ``<SECTION>``. If there is an
1578 alignment constraint on the section's end address then ``__<SECTION>_SIZE__``
1579 corresponds to the size of the section's actual contents, rounded up to the
1580 right boundary. In other words, ``__<SECTION>_SIZE__ = __<SECTION>_END__ - _<SECTION>_START__``. Refer to the value of ``__<SECTION>_UNALIGNED_SIZE__``
1581 to know the actual size of the section's contents.
1585 Size (in bytes) of a given section named ``<SECTION>`` without any padding or
1586 rounding up due to some alignment constraint. In other words,
Dan Handley4def07d2018-03-01 18:44:00 +00001589Some of the linker symbols are mandatory as TF-A code relies on them to be
1590defined. They are listed in the following subsections. Some of them must be
1591provided for each bootloader stage and some are specific to a given bootloader
Douglas Raillard6f625742017-06-28 15:23:03 +01001593
1594The linker scripts define some extra, optional symbols. They are not actually
1595used by any code but they help in understanding the bootloader images' memory
1596layout as they are easy to spot in the link map files.
1598Common linker symbols
1601All BL images share the following requirements:
1603- The BSS section must be zero-initialised before executing any C code.
1604- The coherent memory section (if enabled) must be zero-initialised as well.
1605- The MMU setup code needs to know the extents of the coherent and read-only
1606 memory regions to set the right memory attributes. When
1607 ``SEPARATE_CODE_AND_RODATA=1``, it needs to know more specifically how the
1608 read-only memory region is divided between code and data.
1610The following linker symbols are defined for this purpose:
1612- ``__BSS_START__``
1613- ``__BSS_SIZE__``
1614- ``__COHERENT_RAM_START__`` Must be aligned on a page-size boundary.
1615- ``__COHERENT_RAM_END__`` Must be aligned on a page-size boundary.
1617- ``__RO_START__``
1618- ``__RO_END__``
1619- ``__TEXT_START__``
1620- ``__TEXT_END__``
1621- ``__RODATA_START__``
1622- ``__RODATA_END__``
1624BL1's linker symbols
1627BL1 being the ROM image, it has additional requirements. BL1 resides in ROM and
1628it is entirely executed in place but it needs some read-write memory for its
1629mutable data. Its ``.data`` section (i.e. its allocated read-write data) must be
1630relocated from ROM to RAM before executing any C code.
1632The following additional linker symbols are defined for BL1:
1634- ``__BL1_ROM_END__`` End address of BL1's ROM contents, covering its code
1635 and ``.data`` section in ROM.
1636- ``__DATA_ROM_START__`` Start address of the ``.data`` section in ROM. Must be
1637 aligned on a 16-byte boundary.
1638- ``__DATA_RAM_START__`` Address in RAM where the ``.data`` section should be
1639 copied over. Must be aligned on a 16-byte boundary.
1640- ``__DATA_SIZE__`` Size of the ``.data`` section (in ROM or RAM).
1641- ``__BL1_RAM_START__`` Start address of BL1 read-write data.
1642- ``__BL1_RAM_END__`` End address of BL1 read-write data.
1644How to choose the right base addresses for each bootloader stage image
Dan Handley4def07d2018-03-01 18:44:00 +00001647There is currently no support for dynamic image loading in TF-A. This means
1648that all bootloader images need to be linked against their ultimate runtime
1649locations and the base addresses of each image must be chosen carefully such
1650that images don't overlap each other in an undesired way. As the code grows,
1651the base addresses might need adjustments to cope with the new memory layout.
Douglas Raillard6f625742017-06-28 15:23:03 +01001652
1653The memory layout is completely specific to the platform and so there is no
1654general recipe for choosing the right base addresses for each bootloader image.
1655However, there are tools to aid in understanding the memory layout. These are
1656the link map files: ``build/<platform>/<build-type>/bl<x>/bl<x>.map``, with ``<x>``
1657being the stage bootloader. They provide a detailed view of the memory usage of
1658each image. Among other useful information, they provide the end address of
1659each image.
1661- ```` link map file provides ``__BL1_RAM_END__`` address.
1662- ```` link map file provides ``__BL2_END__`` address.
1663- ```` link map file provides ``__BL31_END__`` address.
1664- ```` link map file provides ``__BL32_END__`` address.
1666For each bootloader image, the platform code must provide its start address
1667as well as a limit address that it must not overstep. The latter is used in the
1668linker scripts to check that the image doesn't grow past that address. If that
1669happens, the linker will issue a message similar to the following:
1673 aarch64-none-elf-ld: BLx has exceeded its limit.
1675Additionally, if the platform memory layout implies some image overlaying like
1676on FVP, BL31 and TSP need to know the limit address that their PROGBITS
1677sections must not overstep. The platform code must provide those.
Soby Mathew509af922018-09-27 16:46:41 +01001679TF-A does not provide any mechanism to verify at boot time that the memory
1680to load a new image is free to prevent overwriting a previously loaded image.
1681The platform must specify the memory available in the system for all the
1682relevant BL images to be loaded.
Douglas Raillard6f625742017-06-28 15:23:03 +01001683
1684For example, in the case of BL1 loading BL2, ``bl1_plat_sec_mem_layout()`` will
1685return the region defined by the platform where BL1 intends to load BL2. The
1686``load_image()`` function performs bounds check for the image size based on the
1687base and maximum image size provided by the platforms. Platforms must take
1688this behaviour into account when defining the base/size for each of the images.
Dan Handley4def07d2018-03-01 18:44:00 +00001690Memory layout on Arm development platforms
Douglas Raillard6f625742017-06-28 15:23:03 +01001691^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Dan Handley4def07d2018-03-01 18:44:00 +00001693The following list describes the memory layout on the Arm development platforms:
Douglas Raillard6f625742017-06-28 15:23:03 +01001694
1695- A 4KB page of shared memory is used for communication between Trusted
1696 Firmware and the platform's power controller. This is located at the base of
1697 Trusted SRAM. The amount of Trusted SRAM available to load the bootloader
1698 images is reduced by the size of the shared memory.
1700 The shared memory is used to store the CPUs' entrypoint mailbox. On Juno,
1701 this is also used for the MHU payload when passing messages to and from the
1702 SCP.
Soby Mathew0f57fab2018-06-06 16:03:10 +01001704- Another 4 KB page is reserved for passing memory layout between BL1 and BL2
1705 and also the dynamic firmware configurations.
Douglas Raillard6f625742017-06-28 15:23:03 +01001707- On FVP, BL1 is originally sitting in the Trusted ROM at address ``0x0``. On
1708 Juno, BL1 resides in flash memory at address ``0x0BEC0000``. BL1 read-write
1709 data are relocated to the top of Trusted SRAM at runtime.
Soby Mathew0f57fab2018-06-06 16:03:10 +01001711- BL2 is loaded below BL1 RW
Sandrine Bailleuxf3cacad2019-02-08 15:26:36 +01001713- EL3 Runtime Software, BL31 for AArch64 and BL32 for AArch32 (e.g. SP_MIN),
Douglas Raillard6f625742017-06-28 15:23:03 +01001714 is loaded at the top of the Trusted SRAM, such that its NOBITS sections will
Soby Mathew0f57fab2018-06-06 16:03:10 +01001715 overwrite BL1 R/W data and BL2. This implies that BL1 global variables
1716 remain valid only until execution reaches the EL3 Runtime Software entry
1717 point during a cold boot.
Douglas Raillard6f625742017-06-28 15:23:03 +01001718
Sandrine Bailleuxf3cacad2019-02-08 15:26:36 +01001719- On Juno, SCP_BL2 is loaded temporarily into the EL3 Runtime Software memory
Paul Beesleybe653a62019-10-04 16:17:46 +00001720 region and transferred to the SCP before being overwritten by EL3 Runtime
Douglas Raillard6f625742017-06-28 15:23:03 +01001721 Software.
1723- BL32 (for AArch64) can be loaded in one of the following locations:
1725 - Trusted SRAM
1726 - Trusted DRAM (FVP only)
1727 - Secure region of DRAM (top 16MB of DRAM configured by the TrustZone
1728 controller)
Soby Mathew0f57fab2018-06-06 16:03:10 +01001730 When BL32 (for AArch64) is loaded into Trusted SRAM, it is loaded below
1731 BL31.
Douglas Raillard6f625742017-06-28 15:23:03 +01001732
Douglas Raillard6f625742017-06-28 15:23:03 +01001733The location of the BL32 image will result in different memory maps. This is
1734illustrated for both FVP and Juno in the following diagrams, using the TSP as
1735an example.
Paul Beesleye1c50262019-03-13 16:20:44 +00001737.. note::
1738 Loading the BL32 image in TZC secured DRAM doesn't change the memory
1739 layout of the other images in Trusted SRAM.
Douglas Raillard6f625742017-06-28 15:23:03 +01001740
Sathees Balya5b8d50e2018-11-15 14:22:30 +00001741CONFIG section in memory layouts shown below contains:
1745 +--------------------+
1746 |bl2_mem_params_descs|
1747 |--------------------|
1748 | fw_configs |
1749 +--------------------+
1751``bl2_mem_params_descs`` contains parameters passed from BL2 to next the
1752BL image during boot.
Manish V Badarkhe089fc622020-06-13 09:42:28 +01001754``fw_configs`` includes soc_fw_config, tos_fw_config, tb_fw_config and fw_config.
Sathees Balya5b8d50e2018-11-15 14:22:30 +00001755
Soby Mathew0f57fab2018-06-06 16:03:10 +01001756**FVP with TSP in Trusted SRAM with firmware configs :**
Douglas Raillard6f625742017-06-28 15:23:03 +01001757(These diagrams only cover the AArch64 case)
Soby Mathew0f57fab2018-06-06 16:03:10 +01001761 DRAM
1762 0xffffffff +----------+
1763 : :
Manish V Badarkheb4a87832022-04-12 21:11:56 +01001764 0x82100000 |----------|
Soby Mathew0f57fab2018-06-06 16:03:10 +01001765 |HW_CONFIG |
Manish V Badarkheb4a87832022-04-12 21:11:56 +01001766 0x82000000 |----------| (non-secure)
Soby Mathew0f57fab2018-06-06 16:03:10 +01001767 | |
1768 0x80000000 +----------+
Manish V Badarkheb4a87832022-04-12 21:11:56 +01001770 Trusted DRAM
1771 0x08000000 +----------+
1772 |HW_CONFIG |
1773 0x07f00000 |----------|
1774 : :
1775 | |
1776 0x06000000 +----------+
Douglas Raillard6f625742017-06-28 15:23:03 +01001778 Trusted SRAM
Soby Mathew0f57fab2018-06-06 16:03:10 +01001779 0x04040000 +----------+ loaded by BL2 +----------------+
1780 | BL1 (rw) | <<<<<<<<<<<<< | |
1781 |----------| <<<<<<<<<<<<< | BL31 NOBITS |
1782 | BL2 | <<<<<<<<<<<<< | |
Douglas Raillard6f625742017-06-28 15:23:03 +01001783 |----------| <<<<<<<<<<<<< |----------------|
1784 | | <<<<<<<<<<<<< | BL31 PROGBITS |
Soby Mathew0f57fab2018-06-06 16:03:10 +01001785 | | <<<<<<<<<<<<< |----------------|
1786 | | <<<<<<<<<<<<< | BL32 |
Manish V Badarkhe089fc622020-06-13 09:42:28 +01001787 0x04003000 +----------+ +----------------+
Sathees Balya5b8d50e2018-11-15 14:22:30 +00001788 | CONFIG |
Soby Mathew0f57fab2018-06-06 16:03:10 +01001789 0x04001000 +----------+
Douglas Raillard6f625742017-06-28 15:23:03 +01001790 | Shared |
1791 0x04000000 +----------+
1793 Trusted ROM
1794 0x04000000 +----------+
1795 | BL1 (ro) |
1796 0x00000000 +----------+
Soby Mathew0f57fab2018-06-06 16:03:10 +01001798**FVP with TSP in Trusted DRAM with firmware configs (default option):**
Douglas Raillard6f625742017-06-28 15:23:03 +01001799
Soby Mathewb2a68f82018-02-16 14:52:52 +00001802 DRAM
1803 0xffffffff +--------------+
1804 : :
Manish V Badarkheb4a87832022-04-12 21:11:56 +01001805 0x82100000 |--------------|
Soby Mathewb2a68f82018-02-16 14:52:52 +00001806 | HW_CONFIG |
Manish V Badarkheb4a87832022-04-12 21:11:56 +01001807 0x82000000 |--------------| (non-secure)
Soby Mathewb2a68f82018-02-16 14:52:52 +00001808 | |
1809 0x80000000 +--------------+
Douglas Raillard6f625742017-06-28 15:23:03 +01001810
Manish V Badarkheb4a87832022-04-12 21:11:56 +01001811 Trusted DRAM
Soby Mathewb2a68f82018-02-16 14:52:52 +00001812 0x08000000 +--------------+
Manish V Badarkheb4a87832022-04-12 21:11:56 +01001813 | HW_CONFIG |
1814 0x07f00000 |--------------|
1815 : :
1816 | BL32 |
Soby Mathewb2a68f82018-02-16 14:52:52 +00001817 0x06000000 +--------------+
Douglas Raillard6f625742017-06-28 15:23:03 +01001818
Soby Mathewb2a68f82018-02-16 14:52:52 +00001819 Trusted SRAM
Soby Mathew0f57fab2018-06-06 16:03:10 +01001820 0x04040000 +--------------+ loaded by BL2 +----------------+
1821 | BL1 (rw) | <<<<<<<<<<<<< | |
1822 |--------------| <<<<<<<<<<<<< | BL31 NOBITS |
1823 | BL2 | <<<<<<<<<<<<< | |
Soby Mathewb2a68f82018-02-16 14:52:52 +00001824 |--------------| <<<<<<<<<<<<< |----------------|
1825 | | <<<<<<<<<<<<< | BL31 PROGBITS |
Soby Mathew0f57fab2018-06-06 16:03:10 +01001826 | | +----------------+
Manish V Badarkhe089fc622020-06-13 09:42:28 +01001827 0x04003000 +--------------+
Sathees Balya5b8d50e2018-11-15 14:22:30 +00001828 | CONFIG |
Soby Mathewb2a68f82018-02-16 14:52:52 +00001829 0x04001000 +--------------+
1830 | Shared |
1831 0x04000000 +--------------+
1833 Trusted ROM
1834 0x04000000 +--------------+
1835 | BL1 (ro) |
1836 0x00000000 +--------------+
Douglas Raillard6f625742017-06-28 15:23:03 +01001837
Soby Mathew0f57fab2018-06-06 16:03:10 +01001838**FVP with TSP in TZC-Secured DRAM with firmware configs :**
Douglas Raillard6f625742017-06-28 15:23:03 +01001839
1842 DRAM
1843 0xffffffff +----------+
Soby Mathewb2a68f82018-02-16 14:52:52 +00001844 | BL32 | (secure)
Douglas Raillard6f625742017-06-28 15:23:03 +01001845 0xff000000 +----------+
1846 | |
Manish V Badarkheb4a87832022-04-12 21:11:56 +01001847 0x82100000 |----------|
Soby Mathew0f57fab2018-06-06 16:03:10 +01001848 |HW_CONFIG |
Manish V Badarkheb4a87832022-04-12 21:11:56 +01001849 0x82000000 |----------| (non-secure)
Douglas Raillard6f625742017-06-28 15:23:03 +01001850 | |
1851 0x80000000 +----------+
Manish V Badarkheb4a87832022-04-12 21:11:56 +01001853 Trusted DRAM
1854 0x08000000 +----------+
1855 |HW_CONFIG |
1856 0x7f000000 |----------|
1857 : :
1858 | |
1859 0x06000000 +----------+
Douglas Raillard6f625742017-06-28 15:23:03 +01001861 Trusted SRAM
Soby Mathew0f57fab2018-06-06 16:03:10 +01001862 0x04040000 +----------+ loaded by BL2 +----------------+
1863 | BL1 (rw) | <<<<<<<<<<<<< | |
1864 |----------| <<<<<<<<<<<<< | BL31 NOBITS |
1865 | BL2 | <<<<<<<<<<<<< | |
Douglas Raillard6f625742017-06-28 15:23:03 +01001866 |----------| <<<<<<<<<<<<< |----------------|
1867 | | <<<<<<<<<<<<< | BL31 PROGBITS |
Soby Mathew0f57fab2018-06-06 16:03:10 +01001868 | | +----------------+
Manish V Badarkhe089fc622020-06-13 09:42:28 +01001869 0x04003000 +----------+
Sathees Balya5b8d50e2018-11-15 14:22:30 +00001870 | CONFIG |
Douglas Raillard6f625742017-06-28 15:23:03 +01001871 0x04001000 +----------+
1872 | Shared |
1873 0x04000000 +----------+
1875 Trusted ROM
1876 0x04000000 +----------+
1877 | BL1 (ro) |
1878 0x00000000 +----------+
Soby Mathew0f57fab2018-06-06 16:03:10 +01001880**Juno with BL32 in Trusted SRAM :**
Douglas Raillard6f625742017-06-28 15:23:03 +01001881
1884 Flash0
1885 0x0C000000 +----------+
1886 : :
1887 0x0BED0000 |----------|
1888 | BL1 (ro) |
1889 0x0BEC0000 |----------|
1890 : :
1891 0x08000000 +----------+ BL31 is loaded
1892 after SCP_BL2 has
1893 Trusted SRAM been sent to SCP
Soby Mathew0f57fab2018-06-06 16:03:10 +01001894 0x04040000 +----------+ loaded by BL2 +----------------+
1895 | BL1 (rw) | <<<<<<<<<<<<< | |
1896 |----------| <<<<<<<<<<<<< | BL31 NOBITS |
1897 | BL2 | <<<<<<<<<<<<< | |
Douglas Raillard6f625742017-06-28 15:23:03 +01001898 |----------| <<<<<<<<<<<<< |----------------|
1899 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS |
Chris Kayddc93cb2020-03-12 13:50:26 +00001900 | | <<<<<<<<<<<<< |----------------|
Soby Mathew0f57fab2018-06-06 16:03:10 +01001901 | | <<<<<<<<<<<<< | BL32 |
1902 | | +----------------+
1903 | |
1904 0x04001000 +----------+
Douglas Raillard6f625742017-06-28 15:23:03 +01001905 | MHU |
1906 0x04000000 +----------+
Soby Mathew0f57fab2018-06-06 16:03:10 +01001908**Juno with BL32 in TZC-secured DRAM :**
Douglas Raillard6f625742017-06-28 15:23:03 +01001909
1912 DRAM
1913 0xFFE00000 +----------+
Soby Mathewb2a68f82018-02-16 14:52:52 +00001914 | BL32 | (secure)
Douglas Raillard6f625742017-06-28 15:23:03 +01001915 0xFF000000 |----------|
1916 | |
1917 : : (non-secure)
1918 | |
1919 0x80000000 +----------+
1921 Flash0
1922 0x0C000000 +----------+
1923 : :
1924 0x0BED0000 |----------|
1925 | BL1 (ro) |
1926 0x0BEC0000 |----------|
1927 : :
1928 0x08000000 +----------+ BL31 is loaded
1929 after SCP_BL2 has
1930 Trusted SRAM been sent to SCP
Soby Mathew0f57fab2018-06-06 16:03:10 +01001931 0x04040000 +----------+ loaded by BL2 +----------------+
1932 | BL1 (rw) | <<<<<<<<<<<<< | |
1933 |----------| <<<<<<<<<<<<< | BL31 NOBITS |
1934 | BL2 | <<<<<<<<<<<<< | |
Douglas Raillard6f625742017-06-28 15:23:03 +01001935 |----------| <<<<<<<<<<<<< |----------------|
1936 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS |
Chris Kayddc93cb2020-03-12 13:50:26 +00001937 | | +----------------+
Douglas Raillard6f625742017-06-28 15:23:03 +01001938 0x04001000 +----------+
1939 | MHU |
1940 0x04000000 +----------+
Paul Beesley43f35ef2019-05-29 13:59:40 +01001942.. _firmware_design_fip:
Sathees Balyae36950b2019-01-30 15:56:44 +00001943
Douglas Raillard6f625742017-06-28 15:23:03 +01001944Firmware Image Package (FIP)
1947Using a Firmware Image Package (FIP) allows for packing bootloader images (and
Dan Handley4def07d2018-03-01 18:44:00 +00001948potentially other payloads) into a single archive that can be loaded by TF-A
1949from non-volatile platform storage. A driver to load images from a FIP has
1950been added to the storage layer and allows a package to be read from supported
1951platform storage. A tool to create Firmware Image Packages is also provided
1952and described below.
Douglas Raillard6f625742017-06-28 15:23:03 +01001953
1954Firmware Image Package layout
1957The FIP layout consists of a table of contents (ToC) followed by payload data.
1958The ToC itself has a header followed by one or more table entries. The ToC is
Jett Zhou4069fb52017-11-24 16:03:58 +08001959terminated by an end marker entry, and since the size of the ToC is 0 bytes,
1960the offset equals the total size of the FIP file. All ToC entries describe some
1961payload data that has been appended to the end of the binary package. With the
1962information provided in the ToC entry the corresponding payload data can be
Douglas Raillard6f625742017-06-28 15:23:03 +01001964
1967 ------------------
1968 | ToC Header |
1969 |----------------|
1970 | ToC Entry 0 |
1971 |----------------|
1972 | ToC Entry 1 |
1973 |----------------|
1974 | ToC End Marker |
1975 |----------------|
1976 | |
1977 | Data 0 |
1978 | |
1979 |----------------|
1980 | |
1981 | Data 1 |
1982 | |
1983 ------------------
1985The ToC header and entry formats are described in the header file
1986``include/tools_share/firmware_image_package.h``. This file is used by both the
Dan Handley4def07d2018-03-01 18:44:00 +00001987tool and TF-A.
Douglas Raillard6f625742017-06-28 15:23:03 +01001988
1989The ToC header has the following fields:
1993 `name`: The name of the ToC. This is currently used to validate the header.
1994 `serial_number`: A non-zero number provided by the creation tool
1995 `flags`: Flags associated with this data.
1996 Bits 0-31: Reserved
1997 Bits 32-47: Platform defined
1998 Bits 48-63: Reserved
2000A ToC entry has the following fields:
2004 `uuid`: All files are referred to by a pre-defined Universally Unique
2005 IDentifier [UUID] . The UUIDs are defined in
2006 `include/tools_share/firmware_image_package.h`. The platform translates
2007 the requested image name into the corresponding UUID when accessing the
2008 package.
2009 `offset_address`: The offset address at which the corresponding payload data
2010 can be found. The offset is calculated from the ToC base address.
2011 `size`: The size of the corresponding payload data in bytes.
Etienne Carriered591d762017-08-23 15:43:33 +02002012 `flags`: Flags associated with this entry. None are yet defined.
Douglas Raillard6f625742017-06-28 15:23:03 +01002013
2014Firmware Image Package creation tool
Dan Handley4def07d2018-03-01 18:44:00 +00002017The FIP creation tool can be used to pack specified images into a binary
2018package that can be loaded by TF-A from platform storage. The tool currently
2019only supports packing bootloader images. Additional image definitions can be
2020added to the tool as required.
Douglas Raillard6f625742017-06-28 15:23:03 +01002021
2022The tool can be found in ``tools/fiptool``.
2024Loading from a Firmware Image Package (FIP)
2027The Firmware Image Package (FIP) driver can load images from a binary package on
Dan Handley4def07d2018-03-01 18:44:00 +00002028non-volatile platform storage. For the Arm development platforms, this is
Douglas Raillard6f625742017-06-28 15:23:03 +01002029currently NOR FLASH.
2031Bootloader images are loaded according to the platform policy as specified by
Dan Handley4def07d2018-03-01 18:44:00 +00002032the function ``plat_get_image_source()``. For the Arm development platforms, this
Douglas Raillard6f625742017-06-28 15:23:03 +01002033means the platform will attempt to load images from a Firmware Image Package
2034located at the start of NOR FLASH0.
Dan Handley4def07d2018-03-01 18:44:00 +00002036The Arm development platforms' policy is to only allow loading of a known set of
Douglas Raillard6f625742017-06-28 15:23:03 +01002037images. The platform policy can be modified to allow additional images.
Dan Handley4def07d2018-03-01 18:44:00 +00002039Use of coherent memory in TF-A
Douglas Raillard6f625742017-06-28 15:23:03 +01002041
2042There might be loss of coherency when physical memory with mismatched
2043shareability, cacheability and memory attributes is accessed by multiple CPUs
Dan Handley4def07d2018-03-01 18:44:00 +00002044(refer to section B2.9 of `Arm ARM`_ for more details). This possibility occurs
2045in TF-A during power up/down sequences when coherency, MMU and caches are
2046turned on/off incrementally.
Douglas Raillard6f625742017-06-28 15:23:03 +01002047
Dan Handley4def07d2018-03-01 18:44:00 +00002048TF-A defines coherent memory as a region of memory with Device nGnRE attributes
2049in the translation tables. The translation granule size in TF-A is 4KB. This
2050is the smallest possible size of the coherent memory region.
Douglas Raillard6f625742017-06-28 15:23:03 +01002051
2052By default, all data structures which are susceptible to accesses with
2053mismatched attributes from various CPUs are allocated in a coherent memory
Paul Beesley34760952019-04-12 14:19:42 +01002054region (refer to section 2.1 of :ref:`Porting Guide`). The coherent memory
2055region accesses are Outer Shareable, non-cacheable and they can be accessed with
2056the Device nGnRE attributes when the MMU is turned on. Hence, at the expense of
2057at least an extra page of memory, TF-A is able to work around coherency issues
2058due to mismatched memory attributes.
Douglas Raillard6f625742017-06-28 15:23:03 +01002059
2060The alternative to the above approach is to allocate the susceptible data
2061structures in Normal WriteBack WriteAllocate Inner shareable memory. This
2062approach requires the data structures to be designed so that it is possible to
2063work around the issue of mismatched memory attributes by performing software
2064cache maintenance on them.
Dan Handley4def07d2018-03-01 18:44:00 +00002066Disabling the use of coherent memory in TF-A
Douglas Raillard6f625742017-06-28 15:23:03 +01002068
2069It might be desirable to avoid the cost of allocating coherent memory on
Dan Handley4def07d2018-03-01 18:44:00 +00002070platforms which are memory constrained. TF-A enables inclusion of coherent
2071memory in firmware images through the build flag ``USE_COHERENT_MEM``.
Douglas Raillard6f625742017-06-28 15:23:03 +01002072This flag is enabled by default. It can be disabled to choose the second
2073approach described above.
2075The below sections analyze the data structures allocated in the coherent memory
2076region and the changes required to allocate them in normal memory.
2078Coherent memory usage in PSCI implementation
2081The ``psci_non_cpu_pd_nodes`` data structure stores the platform's power domain
2082tree information for state management of power domains. By default, this data
Dan Handley4def07d2018-03-01 18:44:00 +00002083structure is allocated in the coherent memory region in TF-A because it can be
Paul Beesley8aabea32019-01-11 18:26:51 +00002084accessed by multiple CPUs, either with caches enabled or disabled.
Douglas Raillard6f625742017-06-28 15:23:03 +01002085
2086.. code:: c
2088 typedef struct non_cpu_pwr_domain_node {
2089 /*
2090 * Index of the first CPU power domain node level 0 which has this node
2091 * as its parent.
2092 */
2093 unsigned int cpu_start_idx;
2095 /*
2096 * Number of CPU power domains which are siblings of the domain indexed
2097 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx
2098 * -> cpu_start_idx + ncpus' have this node as their parent.
2099 */
2100 unsigned int ncpus;
2102 /*
2103 * Index of the parent power domain node.
Douglas Raillard6f625742017-06-28 15:23:03 +01002104 */
2105 unsigned int parent_node;
2107 plat_local_state_t local_state;
2109 unsigned char level;
2111 /* For indexing the psci_lock array*/
2112 unsigned char lock_index;
2113 } non_cpu_pd_node_t;
2115In order to move this data structure to normal memory, the use of each of its
2116fields must be analyzed. Fields like ``cpu_start_idx``, ``ncpus``, ``parent_node``
2117``level`` and ``lock_index`` are only written once during cold boot. Hence removing
2118them from coherent memory involves only doing a clean and invalidate of the
2119cache lines after these fields are written.
2121The field ``local_state`` can be concurrently accessed by multiple CPUs in
2122different cache states. A Lamport's Bakery lock ``psci_locks`` is used to ensure
Paul Beesley8aabea32019-01-11 18:26:51 +00002123mutual exclusion to this field and a clean and invalidate is needed after it
Douglas Raillard6f625742017-06-28 15:23:03 +01002124is written.
2126Bakery lock data
2129The bakery lock data structure ``bakery_lock_t`` is allocated in coherent memory
2130and is accessed by multiple CPUs with mismatched attributes. ``bakery_lock_t`` is
2131defined as follows:
2133.. code:: c
2135 typedef struct bakery_lock {
2136 /*
2137 * The lock_data is a bit-field of 2 members:
2138 * Bit[0] : choosing. This field is set when the CPU is
2139 * choosing its bakery number.
2140 * Bits[1 - 15] : number. This is the bakery number allocated.
2141 */
2142 volatile uint16_t lock_data[BAKERY_LOCK_MAX_CPUS];
2143 } bakery_lock_t;
2145It is a characteristic of Lamport's Bakery algorithm that the volatile per-CPU
2146fields can be read by all CPUs but only written to by the owning CPU.
2148Depending upon the data cache line size, the per-CPU fields of the
2149``bakery_lock_t`` structure for multiple CPUs may exist on a single cache line.
2150These per-CPU fields can be read and written during lock contention by multiple
2151CPUs with mismatched memory attributes. Since these fields are a part of the
2152lock implementation, they do not have access to any other locking primitive to
2153safeguard against the resulting coherency issues. As a result, simple software
2154cache maintenance is not enough to allocate them in coherent memory. Consider
2155the following example.
2157CPU0 updates its per-CPU field with data cache enabled. This write updates a
2158local cache line which contains a copy of the fields for other CPUs as well. Now
2159CPU1 updates its per-CPU field of the ``bakery_lock_t`` structure with data cache
2160disabled. CPU1 then issues a DCIVAC operation to invalidate any stale copies of
2161its field in any other cache line in the system. This operation will invalidate
2162the update made by CPU0 as well.
2164To use bakery locks when ``USE_COHERENT_MEM`` is disabled, the lock data structure
2165has been redesigned. The changes utilise the characteristic of Lamport's Bakery
Sandrine Bailleuxf3cacad2019-02-08 15:26:36 +01002166algorithm mentioned earlier. The bakery_lock structure only allocates the memory
Douglas Raillard6f625742017-06-28 15:23:03 +01002167for a single CPU. The macro ``DEFINE_BAKERY_LOCK`` allocates all the bakery locks
2168needed for a CPU into a section ``bakery_lock``. The linker allocates the memory
Sandrine Bailleuxf3cacad2019-02-08 15:26:36 +01002169for other cores by using the total size allocated for the bakery_lock section
2170and multiplying it with (PLATFORM_CORE_COUNT - 1). This enables software to
Douglas Raillard6f625742017-06-28 15:23:03 +01002171perform software cache maintenance on the lock data structure without running
2172into coherency issues associated with mismatched attributes.
2174The bakery lock data structure ``bakery_info_t`` is defined for use when
2175``USE_COHERENT_MEM`` is disabled as follows:
2177.. code:: c
2179 typedef struct bakery_info {
2180 /*
2181 * The lock_data is a bit-field of 2 members:
2182 * Bit[0] : choosing. This field is set when the CPU is
2183 * choosing its bakery number.
2184 * Bits[1 - 15] : number. This is the bakery number allocated.
2185 */
2186 volatile uint16_t lock_data;
2187 } bakery_info_t;
2189The ``bakery_info_t`` represents a single per-CPU field of one lock and
2190the combination of corresponding ``bakery_info_t`` structures for all CPUs in the
2191system represents the complete bakery lock. The view in memory for a system
2192with n bakery locks are:
2196 bakery_lock section start
2197 |----------------|
2198 | `bakery_info_t`| <-- Lock_0 per-CPU field
2199 | Lock_0 | for CPU0
2200 |----------------|
2201 | `bakery_info_t`| <-- Lock_1 per-CPU field
2202 | Lock_1 | for CPU0
2203 |----------------|
2204 | .... |
2205 |----------------|
2206 | `bakery_info_t`| <-- Lock_N per-CPU field
2207 | Lock_N | for CPU0
2208 ------------------
2209 | XXXXX |
2210 | Padding to |
2211 | next Cache WB | <--- Calculate PERCPU_BAKERY_LOCK_SIZE, allocate
2212 | Granule | continuous memory for remaining CPUs.
2213 ------------------
2214 | `bakery_info_t`| <-- Lock_0 per-CPU field
2215 | Lock_0 | for CPU1
2216 |----------------|
2217 | `bakery_info_t`| <-- Lock_1 per-CPU field
2218 | Lock_1 | for CPU1
2219 |----------------|
2220 | .... |
2221 |----------------|
2222 | `bakery_info_t`| <-- Lock_N per-CPU field
2223 | Lock_N | for CPU1
2224 ------------------
2225 | XXXXX |
2226 | Padding to |
2227 | next Cache WB |
2228 | Granule |
2229 ------------------
2231Consider a system of 2 CPUs with 'N' bakery locks as shown above. For an
Sandrine Bailleuxf3cacad2019-02-08 15:26:36 +01002232operation on Lock_N, the corresponding ``bakery_info_t`` in both CPU0 and CPU1
Douglas Raillard6f625742017-06-28 15:23:03 +01002233``bakery_lock`` section need to be fetched and appropriate cache operations need
2234to be performed for each access.
Dan Handley4def07d2018-03-01 18:44:00 +00002236On Arm Platforms, bakery locks are used in psci (``psci_locks``) and power controller
Douglas Raillard6f625742017-06-28 15:23:03 +01002237driver (``arm_lock``).
2239Non Functional Impact of removing coherent memory
2242Removal of the coherent memory region leads to the additional software overhead
2243of performing cache maintenance for the affected data structures. However, since
2244the memory where the data structures are allocated is cacheable, the overhead is
2245mostly mitigated by an increase in performance.
2247There is however a performance impact for bakery locks, due to:
2249- Additional cache maintenance operations, and
2250- Multiple cache line reads for each lock operation, since the bakery locks
2251 for each CPU are distributed across different cache lines.
2253The implementation has been optimized to minimize this additional overhead.
2254Measurements indicate that when bakery locks are allocated in Normal memory, the
2255minimum latency of acquiring a lock is on an average 3-4 micro seconds whereas
2256in Device memory the same is 2 micro seconds. The measurements were done on the
Dan Handley4def07d2018-03-01 18:44:00 +00002257Juno Arm development platform.
Douglas Raillard6f625742017-06-28 15:23:03 +01002258
2259As mentioned earlier, almost a page of memory can be saved by disabling
2260``USE_COHERENT_MEM``. Each platform needs to consider these trade-offs to decide
2261whether coherent memory should be used. If a platform disables
2262``USE_COHERENT_MEM`` and needs to use bakery locks in the porting layer, it can
2263optionally define macro ``PLAT_PERCPU_BAKERY_LOCK_SIZE`` (see the
Paul Beesley34760952019-04-12 14:19:42 +01002264:ref:`Porting Guide`). Refer to the reference platform code for examples.
Douglas Raillard6f625742017-06-28 15:23:03 +01002265
2266Isolating code and read-only data on separate memory pages
Dan Handley4def07d2018-03-01 18:44:00 +00002269In the Armv8-A VMSA, translation table entries include fields that define the
Douglas Raillard6f625742017-06-28 15:23:03 +01002270properties of the target memory region, such as its access permissions. The
2271smallest unit of memory that can be addressed by a translation table entry is
2272a memory page. Therefore, if software needs to set different permissions on two
2273memory regions then it needs to map them using different memory pages.
2275The default memory layout for each BL image is as follows:
2279 | ... |
2280 +-------------------+
2281 | Read-write data |
2282 +-------------------+ Page boundary
2283 | <Padding> |
2284 +-------------------+
2285 | Exception vectors |
2286 +-------------------+ 2 KB boundary
2287 | <Padding> |
2288 +-------------------+
2289 | Read-only data |
2290 +-------------------+
2291 | Code |
2292 +-------------------+ BLx_BASE
Paul Beesleye1c50262019-03-13 16:20:44 +00002294.. note::
2295 The 2KB alignment for the exception vectors is an architectural
2296 requirement.
Douglas Raillard6f625742017-06-28 15:23:03 +01002297
2298The read-write data start on a new memory page so that they can be mapped with
2299read-write permissions, whereas the code and read-only data below are configured
2300as read-only.
2302However, the read-only data are not aligned on a page boundary. They are
2303contiguous to the code. Therefore, the end of the code section and the beginning
2304of the read-only data one might share a memory page. This forces both to be
2305mapped with the same memory attributes. As the code needs to be executable, this
2306means that the read-only data stored on the same memory page as the code are
2307executable as well. This could potentially be exploited as part of a security
2310TF provides the build flag ``SEPARATE_CODE_AND_RODATA`` to isolate the code and
2311read-only data on separate memory pages. This in turn allows independent control
2312of the access permissions for the code and read-only data. In this case,
2313platform code gets a finer-grained view of the image layout and can
2314appropriately map the code region as executable and the read-only data as
2317This has an impact on memory footprint, as padding bytes need to be introduced
Paul Beesley8aabea32019-01-11 18:26:51 +00002318between the code and read-only data to ensure the segregation of the two. To
Douglas Raillard6f625742017-06-28 15:23:03 +01002319limit the memory cost, this flag also changes the memory layout such that the
2320code and exception vectors are now contiguous, like so:
2324 | ... |
2325 +-------------------+
2326 | Read-write data |
2327 +-------------------+ Page boundary
2328 | <Padding> |
2329 +-------------------+
2330 | Read-only data |
2331 +-------------------+ Page boundary
2332 | <Padding> |
2333 +-------------------+
2334 | Exception vectors |
2335 +-------------------+ 2 KB boundary
2336 | <Padding> |
2337 +-------------------+
2338 | Code |
2339 +-------------------+ BLx_BASE
2341With this more condensed memory layout, the separation of read-only data will
2342add zero or one page to the memory footprint of each BL image. Each platform
2343should consider the trade-off between memory footprint and security.
Dan Handley4def07d2018-03-01 18:44:00 +00002345This build flag is disabled by default, minimising memory footprint. On Arm
Douglas Raillard6f625742017-06-28 15:23:03 +01002346platforms, it is enabled.
Jeenu Viswambharan8e743bc2017-09-22 08:32:10 +01002348Publish and Subscribe Framework
2351The Publish and Subscribe Framework allows EL3 components to define and publish
2352events, to which other EL3 components can subscribe.
2354The following macros are provided by the framework:
2356- ``REGISTER_PUBSUB_EVENT(event)``: Defines an event, and takes one argument,
2357 the event name, which must be a valid C identifier. All calls to
2358 ``REGISTER_PUBSUB_EVENT`` macro must be placed in the file
2359 ``pubsub_events.h``.
2361- ``PUBLISH_EVENT_ARG(event, arg)``: Publishes a defined event, by iterating
2362 subscribed handlers and calling them in turn. The handlers will be passed the
2363 parameter ``arg``. The expected use-case is to broadcast an event.
2365- ``PUBLISH_EVENT(event)``: Like ``PUBLISH_EVENT_ARG``, except that the value
2366 ``NULL`` is passed to subscribed handlers.
2368- ``SUBSCRIBE_TO_EVENT(event, handler)``: Registers the ``handler`` to
2369 subscribe to ``event``. The handler will be executed whenever the ``event``
2370 is published.
2372- ``for_each_subscriber(event, subscriber)``: Iterates through all handlers
2373 subscribed for ``event``. ``subscriber`` must be a local variable of type
2374 ``pubsub_cb_t *``, and will point to each subscribed handler in turn during
2375 iteration. This macro can be used for those patterns that none of the
2376 ``PUBLISH_EVENT_*()`` macros cover.
2378Publishing an event that wasn't defined using ``REGISTER_PUBSUB_EVENT`` will
2379result in build error. Subscribing to an undefined event however won't.
2381Subscribed handlers must be of type ``pubsub_cb_t``, with following function
Paul Beesley29c02522019-03-13 15:11:04 +00002384.. code:: c
Jeenu Viswambharan8e743bc2017-09-22 08:32:10 +01002385
2386 typedef void* (*pubsub_cb_t)(const void *arg);
2388There may be arbitrary number of handlers registered to the same event. The
2389order in which subscribed handlers are notified when that event is published is
2390not defined. Subscribed handlers may be executed in any order; handlers should
2391not assume any relative ordering amongst them.
2393Publishing an event on a PE will result in subscribed handlers executing on that
2394PE only; it won't cause handlers to execute on a different PE.
2396Note that publishing an event on a PE blocks until all the subscribed handlers
2397finish executing on the PE.
Dan Handley4def07d2018-03-01 18:44:00 +00002399TF-A generic code publishes and subscribes to some events within. Platform
2400ports are discouraged from subscribing to them. These events may be withdrawn,
2401renamed, or have their semantics altered in the future. Platforms may however
2402register, publish, and subscribe to platform-specific events.
Dimitris Papastamos17b4c0d2017-10-13 15:27:58 +01002403
Jeenu Viswambharan8e743bc2017-09-22 08:32:10 +01002404Publish and Subscribe Example
2407A publisher that wants to publish event ``foo`` would:
2409- Define the event ``foo`` in the ``pubsub_events.h``.
Paul Beesley29c02522019-03-13 15:11:04 +00002411 .. code:: c
Jeenu Viswambharan8e743bc2017-09-22 08:32:10 +01002412
2415- Depending on the nature of event, use one of ``PUBLISH_EVENT_*()`` macros to
2416 publish the event at the appropriate path and time of execution.
2418A subscriber that wants to subscribe to event ``foo`` published above would
Sandrine Bailleux337e2f12019-02-08 10:50:28 +01002421.. code:: c
Jeenu Viswambharan8e743bc2017-09-22 08:32:10 +01002422
Sandrine Bailleux337e2f12019-02-08 10:50:28 +01002423 void *foo_handler(const void *arg)
2424 {
2425 void *result;
Jeenu Viswambharan8e743bc2017-09-22 08:32:10 +01002426
Sandrine Bailleux337e2f12019-02-08 10:50:28 +01002427 /* Do handling ... */
Jeenu Viswambharan8e743bc2017-09-22 08:32:10 +01002428
Sandrine Bailleux337e2f12019-02-08 10:50:28 +01002429 return result;
2430 }
Jeenu Viswambharan8e743bc2017-09-22 08:32:10 +01002431
Sandrine Bailleux337e2f12019-02-08 10:50:28 +01002432 SUBSCRIBE_TO_EVENT(foo, foo_handler);
Jeenu Viswambharan8e743bc2017-09-22 08:32:10 +01002433
Daniel Boulby1dcc28c2018-09-18 11:45:51 +01002434
2435Reclaiming the BL31 initialization code
2438A significant amount of the code used for the initialization of BL31 is never
2439needed again after boot time. In order to reduce the runtime memory
2440footprint, the memory used for this code can be reclaimed after initialization
2441has finished and be used for runtime data.
2443The build option ``RECLAIM_INIT_CODE`` can be set to mark this boot time code
2444with a ``.text.init.*`` attribute which can be filtered and placed suitably
Paul Beesley8aabea32019-01-11 18:26:51 +00002445within the BL image for later reclamation by the platform. The platform can
2446specify the filter and the memory region for this init section in BL31 via the
Daniel Boulby1dcc28c2018-09-18 11:45:51 +01002447plat.ld.S linker script. For example, on the FVP, this section is placed
2448overlapping the secondary CPU stacks so that after the cold boot is done, this
2449memory can be reclaimed for the stacks. The init memory section is initially
Paul Beesley8aabea32019-01-11 18:26:51 +00002450mapped with ``RO``, ``EXECUTE`` attributes. After BL31 initialization has
Daniel Boulby1dcc28c2018-09-18 11:45:51 +01002451completed, the FVP changes the attributes of this section to ``RW``,
2452``EXECUTE_NEVER`` allowing it to be used for runtime data. The memory attributes
2453are changed within the ``bl31_plat_runtime_setup`` platform hook. The init
2454section section can be reclaimed for any data which is accessed after cold
2455boot initialization and it is upto the platform to make the decision.
Paul Beesley34760952019-04-12 14:19:42 +01002457.. _firmware_design_pmf:
Douglas Raillard6f625742017-06-28 15:23:03 +01002459Performance Measurement Framework
2462The Performance Measurement Framework (PMF) facilitates collection of
Dan Handley4def07d2018-03-01 18:44:00 +00002463timestamps by registered services and provides interfaces to retrieve them
2464from within TF-A. A platform can choose to expose appropriate SMCs to
2465retrieve these collected timestamps.
Douglas Raillard6f625742017-06-28 15:23:03 +01002466
2467By default, the global physical counter is used for the timestamp
2468value and is read via ``CNTPCT_EL0``. The framework allows to retrieve
2469timestamps captured by other CPUs.
2471Timestamp identifier format
2474A PMF timestamp is uniquely identified across the system via the
2475timestamp ID or ``tid``. The ``tid`` is composed as follows:
2479 Bits 0-7: The local timestamp identifier.
2480 Bits 8-9: Reserved.
2481 Bits 10-15: The service identifier.
2482 Bits 16-31: Reserved.
2484#. The service identifier. Each PMF service is identified by a
2485 service name and a service identifier. Both the service name and
2486 identifier are unique within the system as a whole.
2488#. The local timestamp identifier. This identifier is unique within a given
2489 service.
2491Registering a PMF service
2494To register a PMF service, the ``PMF_REGISTER_SERVICE()`` macro from ``pmf.h``
2495is used. The arguments required are the service name, the service ID,
2496the total number of local timestamps to be captured and a set of flags.
2498The ``flags`` field can be specified as a bitwise-OR of the following values:
2502 PMF_STORE_ENABLE: The timestamp is stored in memory for later retrieval.
2503 PMF_DUMP_ENABLE: The timestamp is dumped on the serial console.
2505The ``PMF_REGISTER_SERVICE()`` reserves memory to store captured
2506timestamps in a PMF specific linker section at build time.
2507Additionally, it defines necessary functions to capture and
2508retrieve a particular timestamp for the given service at runtime.
Dan Handley4def07d2018-03-01 18:44:00 +00002510The macro ``PMF_REGISTER_SERVICE()`` only enables capturing PMF timestamps
2511from within TF-A. In order to retrieve timestamps from outside of TF-A, the
Douglas Raillard6f625742017-06-28 15:23:03 +01002512``PMF_REGISTER_SERVICE_SMC()`` macro must be used instead. This macro
2513accepts the same set of arguments as the ``PMF_REGISTER_SERVICE()``
2514macro but additionally supports retrieving timestamps using SMCs.
2516Capturing a timestamp
2519PMF timestamps are stored in a per-service timestamp region. On a
2520system with multiple CPUs, each timestamp is captured and stored
2521in a per-CPU cache line aligned memory region.
2523Having registered the service, the ``PMF_CAPTURE_TIMESTAMP()`` macro can be
2524used to capture a timestamp at the location where it is used. The macro
2525takes the service name, a local timestamp identifier and a flag as arguments.
2527The ``flags`` field argument can be zero, or ``PMF_CACHE_MAINT`` which
2528instructs PMF to do cache maintenance following the capture. Cache
2529maintenance is required if any of the service's timestamps are captured
2530with data cache disabled.
2532To capture a timestamp in assembly code, the caller should use
2533``pmf_calc_timestamp_addr`` macro (defined in ``pmf_asm_macros.S``) to
2534calculate the address of where the timestamp would be stored. The
2535caller should then read ``CNTPCT_EL0`` register to obtain the timestamp
2536and store it at the determined address for later retrieval.
2538Retrieving a timestamp
Dan Handley4def07d2018-03-01 18:44:00 +00002541From within TF-A, timestamps for individual CPUs can be retrieved using either
2543These macros accept the CPU's MPIDR value, or its ordinal position
Douglas Raillard6f625742017-06-28 15:23:03 +01002545
Dan Handley4def07d2018-03-01 18:44:00 +00002546From outside TF-A, timestamps for individual CPUs can be retrieved by calling
2547into ``pmf_smc_handler()``.
Douglas Raillard6f625742017-06-28 15:23:03 +01002548
Paul Beesley29c02522019-03-13 15:11:04 +00002549::
Douglas Raillard6f625742017-06-28 15:23:03 +01002550
2551 Interface : pmf_smc_handler()
2552 Argument : unsigned int smc_fid, u_register_t x1,
2553 u_register_t x2, u_register_t x3,
2554 u_register_t x4, void *cookie,
2555 void *handle, u_register_t flags
2556 Return : uintptr_t
2558 smc_fid: Holds the SMC identifier which is either `PMF_SMC_GET_TIMESTAMP_32`
2559 when the caller of the SMC is running in AArch32 mode
2560 or `PMF_SMC_GET_TIMESTAMP_64` when the caller is running in AArch64 mode.
2561 x1: Timestamp identifier.
2562 x2: The `mpidr` of the CPU for which the timestamp has to be retrieved.
2563 This can be the `mpidr` of a different core to the one initiating
2564 the SMC. In that case, service specific cache maintenance may be
2565 required to ensure the updated copy of the timestamp is returned.
2566 x3: A flags value that is either 0 or `PMF_CACHE_MAINT`. If
2567 `PMF_CACHE_MAINT` is passed, then the PMF code will perform a
2568 cache invalidate before reading the timestamp. This ensures
2569 an updated copy is returned.
2571The remaining arguments, ``x4``, ``cookie``, ``handle`` and ``flags`` are unused
2572in this implementation.
2574PMF code structure
2577#. ``pmf_main.c`` consists of core functions that implement service registration,
2578 initialization, storing, dumping and retrieving timestamps.
2580#. ``pmf_smc.c`` contains the SMC handling for registered PMF services.
2582#. ``pmf.h`` contains the public interface to Performance Measurement Framework.
2584#. ``pmf_asm_macros.S`` consists of macros to facilitate capturing timestamps in
2585 assembly code.
2587#. ``pmf_helpers.h`` is an internal header used by ``pmf.h``.
Dan Handley4def07d2018-03-01 18:44:00 +00002589Armv8-A Architecture Extensions
Douglas Raillard6f625742017-06-28 15:23:03 +01002591
Dan Handley4def07d2018-03-01 18:44:00 +00002592TF-A makes use of Armv8-A Architecture Extensions where applicable. This
2593section lists the usage of Architecture Extensions, and build flags
2594controlling them.
Douglas Raillard6f625742017-06-28 15:23:03 +01002595
2596In general, and unless individually mentioned, the build options
Alexei Fedorovfa6f7742019-03-11 16:51:47 +00002597``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` select the Architecture Extension to
Dan Handley4def07d2018-03-01 18:44:00 +00002598target when building TF-A. Subsequent Arm Architecture Extensions are backward
2599compatible with previous versions.
Douglas Raillard6f625742017-06-28 15:23:03 +01002600
2601The build system only requires that ``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` have a
2602valid numeric value. These build options only control whether or not
Dan Handley4def07d2018-03-01 18:44:00 +00002603Architecture Extension-specific code is included in the build. Otherwise, TF-A
2604targets the base Armv8.0-A architecture; i.e. as if ``ARM_ARCH_MAJOR`` == 8
2605and ``ARM_ARCH_MINOR`` == 0, which are also their respective default values.
Douglas Raillard6f625742017-06-28 15:23:03 +01002606
Paul Beesley43f35ef2019-05-29 13:59:40 +01002607.. seealso:: :ref:`Build Options`
Douglas Raillard6f625742017-06-28 15:23:03 +01002608
2609For details on the Architecture Extension and available features, please refer
2610to the respective Architecture Extension Supplement.
Dan Handley4def07d2018-03-01 18:44:00 +00002612Armv8.1-A
Douglas Raillard6f625742017-06-28 15:23:03 +01002614
2615This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` >= 8, or when
2616``ARM_ARCH_MAJOR`` == 8 and ``ARM_ARCH_MINOR`` >= 1.
Soby Mathewc97cba42019-09-25 14:03:41 +01002618- By default, a load-/store-exclusive instruction pair is used to implement
2619 spinlocks. The ``USE_SPINLOCK_CAS`` build option when set to 1 selects the
2620 spinlock implementation using the ARMv8.1-LSE Compare and Swap instruction.
2621 Notice this instruction is only available in AArch64 execution state, so
2622 the option is only available to AArch64 builds.
Douglas Raillard6f625742017-06-28 15:23:03 +01002623
Dan Handley4def07d2018-03-01 18:44:00 +00002624Armv8.2-A
Isla Mitchell9fce2722017-08-07 11:20:13 +01002626
Antonio Nino Diazd71446c2019-02-19 13:14:06 +00002627- The presence of ARMv8.2-TTCNP is detected at runtime. When it is present, the
2628 Common not Private (TTBRn_ELx.CnP) bit is enabled to indicate that multiple
Sandrine Bailleux7c0a8432018-01-29 14:48:15 +01002629 Processing Elements in the same Inner Shareable domain use the same
2630 translation table entries for a given stage of translation for a particular
2631 translation regime.
Isla Mitchell9fce2722017-08-07 11:20:13 +01002632
Jeenu Viswambharan3ff4aaa2018-08-15 14:29:29 +01002633Armv8.3-A
Antonio Nino Diaz52839622019-01-31 11:58:00 +00002636- Pointer authentication features of Armv8.3-A are unconditionally enabled in
2637 the Non-secure world so that lower ELs are allowed to use them without
2638 causing a trap to EL3.
2640 In order to enable the Secure world to use it, ``CTX_INCLUDE_PAUTH_REGS``
2641 must be set to 1. This will add all pointer authentication system registers
2642 to the context that is saved when doing a world switch.
Jeenu Viswambharan3ff4aaa2018-08-15 14:29:29 +01002643
Alexei Fedorov06715f82019-03-13 11:05:07 +00002644 The TF-A itself has support for pointer authentication at runtime
Alexei Fedorov9fc59632019-05-24 12:17:09 +01002645 that can be enabled by setting ``BRANCH_PROTECTION`` option to non-zero and
Antonio Nino Diazb86048c2019-02-19 11:53:51 +00002646 ``CTX_INCLUDE_PAUTH_REGS`` to 1. This enables pointer authentication in BL1,
2647 BL2, BL31, and the TSP if it is used.
Alexei Fedorov06715f82019-03-13 11:05:07 +00002649 Note that Pointer Authentication is enabled for Non-secure world irrespective
2650 of the value of these build flags if the CPU supports it.
Alexei Fedorovfa6f7742019-03-11 16:51:47 +00002652 If ``ARM_ARCH_MAJOR == 8`` and ``ARM_ARCH_MINOR >= 3`` the code footprint of
2653 enabling PAuth is lower because the compiler will use the optimized
2654 PAuth instructions rather than the backwards-compatible ones.
Alexei Fedorov9fc59632019-05-24 12:17:09 +01002656Armv8.5-A
2659- Branch Target Identification feature is selected by ``BRANCH_PROTECTION``
Manish Pandey700e7682021-10-21 21:53:49 +01002660 option set to 1. This option defaults to 0.
Justin Chadwell88d493f2019-07-18 16:16:32 +01002661
2662- Memory Tagging Extension feature is unconditionally enabled for both worlds
2663 (at EL0 and S-EL0) if it is only supported at EL0. If instead it is
2664 implemented at all ELs, it is unconditionally enabled for only the normal
2665 world. To enable it for the secure world as well, the build option
2666 ``CTX_INCLUDE_MTE_REGS`` is required. If the hardware does not implement
2667 MTE support at all, it is always disabled, no matter what build options
2668 are used.
Alexei Fedorov9fc59632019-05-24 12:17:09 +01002669
Dan Handley4def07d2018-03-01 18:44:00 +00002670Armv7-A
Etienne Carriere26e63c42017-11-08 13:48:40 +01002672
2673This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` == 7.
Dan Handley4def07d2018-03-01 18:44:00 +00002675There are several Armv7-A extensions available. Obviously the TrustZone
2676extension is mandatory to support the TF-A bootloader and runtime services.
Etienne Carriere26e63c42017-11-08 13:48:40 +01002677
Dan Handley4def07d2018-03-01 18:44:00 +00002678Platform implementing an Armv7-A system can to define from its target
Etienne Carriere26e63c42017-11-08 13:48:40 +01002679Cortex-A architecture through ``ARM_CORTEX_A<X> = yes`` in their
Paul Beesley8aabea32019-01-11 18:26:51 +00002680```` script. For example ``ARM_CORTEX_A15=yes`` for a
Etienne Carriere26e63c42017-11-08 13:48:40 +01002681Cortex-A15 target.
2683Platform can also set ``ARM_WITH_NEON=yes`` to enable neon support.
Paul Beesleybe653a62019-10-04 16:17:46 +00002684Note that using neon at runtime has constraints on non secure world context.
Dan Handley4def07d2018-03-01 18:44:00 +00002685TF-A does not yet provide VFP context management.
Etienne Carriere26e63c42017-11-08 13:48:40 +01002686
2687Directive ``ARM_CORTEX_A<x>`` and ``ARM_WITH_NEON`` are used to set
2688the toolchain target architecture directive.
2690Platform may choose to not define straight the toolchain target architecture
2691directive by defining ``MARCH32_DIRECTIVE``.
Paul Beesley29c02522019-03-13 15:11:04 +00002694.. code:: make
Etienne Carriere26e63c42017-11-08 13:48:40 +01002695
2696 MARCH32_DIRECTIVE := -mach=armv7-a
Douglas Raillard6f625742017-06-28 15:23:03 +01002698Code Structure
Dan Handley4def07d2018-03-01 18:44:00 +00002701TF-A code is logically divided between the three boot loader stages mentioned
2702in the previous sections. The code is also divided into the following
2703categories (present as directories in the source code):
Douglas Raillard6f625742017-06-28 15:23:03 +01002704
2705- **Platform specific.** Choice of architecture specific code depends upon
2706 the platform.
2707- **Common code.** This is platform and architecture agnostic code.
2708- **Library code.** This code comprises of functionality commonly used by all
2709 other code. The PSCI implementation and other EL3 runtime frameworks reside
2710 as Library components.
2711- **Stage specific.** Code specific to a boot stage.
2712- **Drivers.**
2713- **Services.** EL3 runtime services (eg: SPD). Specific SPD services
2714 reside in the ``services/spd`` directory (e.g. ``services/spd/tspd``).
2716Each boot loader stage uses code from one or more of the above mentioned
2717categories. Based upon the above, the code layout looks like this:
2721 Directory Used by BL1? Used by BL2? Used by BL31?
2722 bl1 Yes No No
2723 bl2 No Yes No
2724 bl31 No No Yes
2725 plat Yes Yes Yes
2726 drivers Yes No Yes
2727 common Yes Yes Yes
2728 lib Yes Yes Yes
2729 services No No Yes
Sandrine Bailleuxf3cacad2019-02-08 15:26:36 +01002731The build system provides a non configurable build option IMAGE_BLx for each
2732boot loader stage (where x = BL stage). e.g. for BL1 , IMAGE_BL1 will be
Dan Handley4def07d2018-03-01 18:44:00 +00002733defined by the build system. This enables TF-A to compile certain code only
2734for specific boot loader stages
Douglas Raillard6f625742017-06-28 15:23:03 +01002735
2736All assembler files have the ``.S`` extension. The linker source files for each
2737boot stage have the extension ``.ld.S``. These are processed by GCC to create the
2738linker scripts which have the extension ``.ld``.
2740FDTs provide a description of the hardware platform and are used by the Linux
2741kernel at boot time. These can be found in the ``fdts`` directory.
Paul Beesley34760952019-04-12 14:19:42 +01002743.. rubric:: References
Douglas Raillard6f625742017-06-28 15:23:03 +01002744
Paul Beesley34760952019-04-12 14:19:42 +01002745- `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D)`_
2747- `Power State Coordination Interface PDD`_
Sandrine Bailleux71ac9312020-04-17 14:06:52 +02002749- `SMC Calling Convention`_
Paul Beesley34760952019-04-12 14:19:42 +01002750
2751- :ref:`Interrupt Management Framework`
Douglas Raillard6f625742017-06-28 15:23:03 +01002752
Manish V Badarkheb4a87832022-04-12 21:11:56 +01002755*Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.*
Douglas Raillard6f625742017-06-28 15:23:03 +01002756
Paul Beesley34760952019-04-12 14:19:42 +01002757.. _Power State Coordination Interface PDD:
laurenw-arm3ba55a32020-04-16 10:02:17 -05002758.. _SMCCC:
Douglas Raillard6f625742017-06-28 15:23:03 +01002759.. _PSCI:
2760.. _Power State Coordination Interface PDD:
Petre-Ionut Tudor62c9be72019-09-27 15:13:21 +01002761.. _Arm ARM:
laurenw-arm3ba55a32020-04-16 10:02:17 -05002762.. _SMC Calling Convention:
Sandrine Bailleuxc1491eb2019-04-24 10:41:24 +02002763.. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D):
Zelalem Aweke7446c262021-10-21 13:59:45 -05002764.. _Arm Confidential Compute Architecture (Arm CCA):
Douglas Raillard6f625742017-06-28 15:23:03 +01002765
Paul Beesleya2c320a2019-03-13 15:49:27 +00002766.. |Image 1| image:: ../resources/diagrams/rt-svc-descs-layout.png