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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Jeenu Viswambharan10bcd762017-01-03 11:01:51 +00002 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __ARCH_H__
32#define __ARCH_H__
33
Scott Branden53d9c9c2017-04-10 11:45:52 -070034#include <utils_def.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010035
36/*******************************************************************************
37 * MIDR bit definitions
38 ******************************************************************************/
Soby Mathew9b476842014-08-14 11:33:56 +010039#define MIDR_IMPL_MASK 0xff
40#define MIDR_IMPL_SHIFT 0x18
Soby Mathewd9bdaf22014-08-14 16:19:29 +010041#define MIDR_VAR_SHIFT 20
Soby Mathew7395a722014-09-22 12:11:36 +010042#define MIDR_VAR_BITS 4
Jeenu Viswambharan10bcd762017-01-03 11:01:51 +000043#define MIDR_VAR_MASK 0xf
Soby Mathewd9bdaf22014-08-14 16:19:29 +010044#define MIDR_REV_SHIFT 0
Soby Mathew7395a722014-09-22 12:11:36 +010045#define MIDR_REV_BITS 4
Jeenu Viswambharan10bcd762017-01-03 11:01:51 +000046#define MIDR_REV_MASK 0xf
Achin Gupta4f6ad662013-10-25 09:08:21 +010047#define MIDR_PN_MASK 0xfff
48#define MIDR_PN_SHIFT 0x4
Achin Gupta4f6ad662013-10-25 09:08:21 +010049
50/*******************************************************************************
51 * MPIDR macros
52 ******************************************************************************/
Summer Qind8d6cf22017-02-28 16:46:17 +000053#define MPIDR_MT_MASK (1 << 24)
Achin Gupta4f6ad662013-10-25 09:08:21 +010054#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
55#define MPIDR_CLUSTER_MASK MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS
56#define MPIDR_AFFINITY_BITS 8
57#define MPIDR_AFFLVL_MASK 0xff
58#define MPIDR_AFF0_SHIFT 0
59#define MPIDR_AFF1_SHIFT 8
60#define MPIDR_AFF2_SHIFT 16
61#define MPIDR_AFF3_SHIFT 32
62#define MPIDR_AFFINITY_MASK 0xff00ffffff
63#define MPIDR_AFFLVL_SHIFT 3
64#define MPIDR_AFFLVL0 0
65#define MPIDR_AFFLVL1 1
66#define MPIDR_AFFLVL2 2
67#define MPIDR_AFFLVL3 3
Vikram Kanigiri4991ecd2015-02-26 15:25:58 +000068#define MPIDR_AFFLVL0_VAL(mpidr) \
69 ((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
70#define MPIDR_AFFLVL1_VAL(mpidr) \
71 ((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
72#define MPIDR_AFFLVL2_VAL(mpidr) \
73 ((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
74#define MPIDR_AFFLVL3_VAL(mpidr) \
75 ((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK)
Soby Mathew235585b2014-12-04 14:14:12 +000076/*
77 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
78 * add one while using this macro to define array sizes.
79 * TODO: Support only the first 3 affinity levels for now.
80 */
Achin Gupta4f6ad662013-10-25 09:08:21 +010081#define MPIDR_MAX_AFFLVL 2
82
83/* Constant to highlight the assumption that MPIDR allocation starts from 0 */
84#define FIRST_MPIDR 0
85
86/*******************************************************************************
Andrew Thoelke5c3272a2014-06-02 15:44:43 +010087 * Definitions for CPU system register interface to GICv3
88 ******************************************************************************/
89#define ICC_SRE_EL1 S3_0_C12_C12_5
90#define ICC_SRE_EL2 S3_4_C12_C9_5
91#define ICC_SRE_EL3 S3_6_C12_C12_5
92#define ICC_CTLR_EL1 S3_0_C12_C12_4
93#define ICC_CTLR_EL3 S3_6_C12_C12_4
94#define ICC_PMR_EL1 S3_0_C4_C6_0
Achin Guptadf373732015-09-03 14:18:02 +010095#define ICC_IGRPEN1_EL3 S3_6_c12_c12_7
96#define ICC_IGRPEN0_EL1 S3_0_c12_c12_6
97#define ICC_HPPIR0_EL1 S3_0_c12_c8_2
98#define ICC_HPPIR1_EL1 S3_0_c12_c12_2
99#define ICC_IAR0_EL1 S3_0_c12_c8_0
100#define ICC_IAR1_EL1 S3_0_c12_c12_0
101#define ICC_EOIR0_EL1 S3_0_c12_c8_1
102#define ICC_EOIR1_EL1 S3_0_c12_c12_1
Andrew Thoelke5c3272a2014-06-02 15:44:43 +0100103
104/*******************************************************************************
Achin Guptac2b43af2013-10-31 11:27:43 +0000105 * Generic timer memory mapped registers & offsets
106 ******************************************************************************/
107#define CNTCR_OFF 0x000
108#define CNTFID_OFF 0x020
109
110#define CNTCR_EN (1 << 0)
111#define CNTCR_HDBG (1 << 1)
Sandrine Bailleux9e864902014-03-31 11:25:18 +0100112#define CNTCR_FCREQ(x) ((x) << 8)
Achin Guptac2b43af2013-10-31 11:27:43 +0000113
114/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100115 * System register bit definitions
116 ******************************************************************************/
117/* CLIDR definitions */
118#define LOUIS_SHIFT 21
119#define LOC_SHIFT 24
120#define CLIDR_FIELD_WIDTH 3
121
122/* CSSELR definitions */
123#define LEVEL_SHIFT 1
124
125/* D$ set/way op type defines */
126#define DCISW 0x0
127#define DCCISW 0x1
128#define DCCSW 0x2
129
130/* ID_AA64PFR0_EL1 definitions */
131#define ID_AA64PFR0_EL0_SHIFT 0
132#define ID_AA64PFR0_EL1_SHIFT 4
133#define ID_AA64PFR0_EL2_SHIFT 8
134#define ID_AA64PFR0_EL3_SHIFT 12
135#define ID_AA64PFR0_ELX_MASK 0xf
136
Jeenu Viswambharanf4c8aa92017-02-21 14:40:44 +0000137#define EL_IMPL_NONE 0
138#define EL_IMPL_A64ONLY 1
139#define EL_IMPL_A64_A32 2
140
Achin Guptadf373732015-09-03 14:18:02 +0100141#define ID_AA64PFR0_GIC_SHIFT 24
142#define ID_AA64PFR0_GIC_WIDTH 4
143#define ID_AA64PFR0_GIC_MASK ((1 << ID_AA64PFR0_GIC_WIDTH) - 1)
144
Antonio Nino Diaz00296242016-12-13 15:28:54 +0000145/* ID_AA64MMFR0_EL1 definitions */
146#define ID_AA64MMFR0_EL1_PARANGE_MASK 0xf
147
148#define PARANGE_0000 32
149#define PARANGE_0001 36
150#define PARANGE_0010 40
151#define PARANGE_0011 42
152#define PARANGE_0100 44
153#define PARANGE_0101 48
154
Achin Gupta4f6ad662013-10-25 09:08:21 +0100155/* ID_PFR1_EL1 definitions */
156#define ID_PFR1_VIRTEXT_SHIFT 12
157#define ID_PFR1_VIRTEXT_MASK 0xf
158#define GET_VIRT_EXT(id) ((id >> ID_PFR1_VIRTEXT_SHIFT) \
159 & ID_PFR1_VIRTEXT_MASK)
160
161/* SCTLR definitions */
162#define SCTLR_EL2_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \
163 (1 << 18) | (1 << 16) | (1 << 11) | (1 << 5) | \
164 (1 << 4))
165
166#define SCTLR_EL1_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \
Vikram Kanigiri6cd12da2015-07-22 11:53:52 +0100167 (1 << 20) | (1 << 11))
Jens Wiklanderae213ce2014-09-04 10:23:27 +0200168#define SCTLR_AARCH32_EL1_RES1 \
169 ((1 << 23) | (1 << 22) | (1 << 11) | (1 << 4) | \
170 (1 << 3))
171
Achin Gupta4f6ad662013-10-25 09:08:21 +0100172#define SCTLR_M_BIT (1 << 0)
173#define SCTLR_A_BIT (1 << 1)
174#define SCTLR_C_BIT (1 << 2)
175#define SCTLR_SA_BIT (1 << 3)
Soby Mathewb7b07872016-09-29 14:15:57 +0100176#define SCTLR_CP15BEN_BIT (1 << 5)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100177#define SCTLR_I_BIT (1 << 12)
Soby Mathewb7b07872016-09-29 14:15:57 +0100178#define SCTLR_NTWI_BIT (1 << 16)
179#define SCTLR_NTWE_BIT (1 << 18)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100180#define SCTLR_WXN_BIT (1 << 19)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100181#define SCTLR_EE_BIT (1 << 25)
182
Achin Gupta4f6ad662013-10-25 09:08:21 +0100183/* CPACR_El1 definitions */
184#define CPACR_EL1_FPEN(x) (x << 20)
185#define CPACR_EL1_FP_TRAP_EL0 0x1
186#define CPACR_EL1_FP_TRAP_ALL 0x2
187#define CPACR_EL1_FP_TRAP_NONE 0x3
188
189/* SCR definitions */
190#define SCR_RES1_BITS ((1 << 4) | (1 << 5))
191#define SCR_TWE_BIT (1 << 13)
192#define SCR_TWI_BIT (1 << 12)
193#define SCR_ST_BIT (1 << 11)
194#define SCR_RW_BIT (1 << 10)
195#define SCR_SIF_BIT (1 << 9)
196#define SCR_HCE_BIT (1 << 8)
197#define SCR_SMD_BIT (1 << 7)
198#define SCR_EA_BIT (1 << 3)
199#define SCR_FIQ_BIT (1 << 2)
200#define SCR_IRQ_BIT (1 << 1)
201#define SCR_NS_BIT (1 << 0)
Achin Guptac429b5e2014-05-04 18:38:28 +0100202#define SCR_VALID_BIT_MASK 0x2f8f
Achin Gupta4f6ad662013-10-25 09:08:21 +0100203
dp-arm85e93ba2017-02-08 11:51:50 +0000204/* MDCR definitions */
205#define MDCR_SPD32(x) ((x) << 14)
206#define MDCR_SPD32_LEGACY 0x0
207#define MDCR_SPD32_DISABLE 0x2
208#define MDCR_SPD32_ENABLE 0x3
209#define MDCR_SDD_BIT (1 << 16)
210
211#define MDCR_DEF_VAL (MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE))
212
Achin Gupta4f6ad662013-10-25 09:08:21 +0100213/* HCR definitions */
214#define HCR_RW_BIT (1ull << 31)
215#define HCR_AMO_BIT (1 << 5)
216#define HCR_IMO_BIT (1 << 4)
217#define HCR_FMO_BIT (1 << 3)
218
Gerald Lejeune6b836cf2016-03-22 11:11:46 +0100219/* ISR definitions */
220#define ISR_A_SHIFT 8
221#define ISR_I_SHIFT 7
222#define ISR_F_SHIFT 6
223
Achin Gupta4f6ad662013-10-25 09:08:21 +0100224/* CNTHCTL_EL2 definitions */
Andrew Thoelke167a9352014-06-04 21:10:52 +0100225#define EVNTEN_BIT (1 << 2)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100226#define EL1PCEN_BIT (1 << 1)
227#define EL1PCTEN_BIT (1 << 0)
228
229/* CNTKCTL_EL1 definitions */
230#define EL0PTEN_BIT (1 << 9)
231#define EL0VTEN_BIT (1 << 8)
232#define EL0PCTEN_BIT (1 << 0)
233#define EL0VCTEN_BIT (1 << 1)
Sandrine Bailleux01b916b2014-07-17 16:06:39 +0100234#define EVNTEN_BIT (1 << 2)
235#define EVNTDIR_BIT (1 << 3)
236#define EVNTI_SHIFT 4
237#define EVNTI_MASK 0xf
Achin Gupta4f6ad662013-10-25 09:08:21 +0100238
239/* CPTR_EL3 definitions */
Harry Liebel4f603682014-01-14 18:11:48 +0000240#define TCPAC_BIT (1 << 31)
241#define TTA_BIT (1 << 20)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100242#define TFP_BIT (1 << 10)
243
244/* CPSR/SPSR definitions */
245#define DAIF_FIQ_BIT (1 << 0)
246#define DAIF_IRQ_BIT (1 << 1)
247#define DAIF_ABT_BIT (1 << 2)
248#define DAIF_DBG_BIT (1 << 3)
Vikram Kanigiri23ff9ba2014-05-13 14:42:08 +0100249#define SPSR_DAIF_SHIFT 6
250#define SPSR_DAIF_MASK 0xf
251
252#define SPSR_AIF_SHIFT 6
253#define SPSR_AIF_MASK 0x7
254
255#define SPSR_E_SHIFT 9
256#define SPSR_E_MASK 0x1
257#define SPSR_E_LITTLE 0x0
258#define SPSR_E_BIG 0x1
259
260#define SPSR_T_SHIFT 5
261#define SPSR_T_MASK 0x1
262#define SPSR_T_ARM 0x0
263#define SPSR_T_THUMB 0x1
264
265#define DISABLE_ALL_EXCEPTIONS \
266 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
267
Yatharth Kochar07570d52016-11-14 12:01:04 +0000268/*
269 * RMR_EL3 definitions
270 */
271#define RMR_EL3_RR_BIT (1 << 1)
272#define RMR_EL3_AA64_BIT (1 << 0)
273
274/*
275 * HI-VECTOR address for AArch32 state
276 */
277#define HI_VECTOR_BASE (0xFFFF0000)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100278
279/*
280 * TCR defintions
281 */
282#define TCR_EL3_RES1 ((1UL << 31) | (1UL << 23))
Lin Ma73ad2572014-06-27 16:56:30 -0700283#define TCR_EL1_IPS_SHIFT 32
284#define TCR_EL3_PS_SHIFT 16
Achin Gupta4f6ad662013-10-25 09:08:21 +0100285
Antonio Nino Diaze8719552016-08-02 09:21:41 +0100286#define TCR_TxSZ_MIN 16
287#define TCR_TxSZ_MAX 39
288
Lin Ma73ad2572014-06-27 16:56:30 -0700289/* (internal) physical address size bits in EL3/EL1 */
290#define TCR_PS_BITS_4GB (0x0)
291#define TCR_PS_BITS_64GB (0x1)
292#define TCR_PS_BITS_1TB (0x2)
293#define TCR_PS_BITS_4TB (0x3)
294#define TCR_PS_BITS_16TB (0x4)
295#define TCR_PS_BITS_256TB (0x5)
296
297#define ADDR_MASK_48_TO_63 0xFFFF000000000000UL
298#define ADDR_MASK_44_TO_47 0x0000F00000000000UL
299#define ADDR_MASK_42_TO_43 0x00000C0000000000UL
300#define ADDR_MASK_40_TO_41 0x0000030000000000UL
301#define ADDR_MASK_36_TO_39 0x000000F000000000UL
302#define ADDR_MASK_32_TO_35 0x0000000F00000000UL
Achin Gupta4f6ad662013-10-25 09:08:21 +0100303
304#define TCR_RGN_INNER_NC (0x0 << 8)
305#define TCR_RGN_INNER_WBA (0x1 << 8)
306#define TCR_RGN_INNER_WT (0x2 << 8)
307#define TCR_RGN_INNER_WBNA (0x3 << 8)
308
309#define TCR_RGN_OUTER_NC (0x0 << 10)
310#define TCR_RGN_OUTER_WBA (0x1 << 10)
311#define TCR_RGN_OUTER_WT (0x2 << 10)
312#define TCR_RGN_OUTER_WBNA (0x3 << 10)
313
314#define TCR_SH_NON_SHAREABLE (0x0 << 12)
315#define TCR_SH_OUTER_SHAREABLE (0x2 << 12)
316#define TCR_SH_INNER_SHAREABLE (0x3 << 12)
317
Vikram Kanigiri23ff9ba2014-05-13 14:42:08 +0100318#define MODE_SP_SHIFT 0x0
319#define MODE_SP_MASK 0x1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100320#define MODE_SP_EL0 0x0
321#define MODE_SP_ELX 0x1
Vikram Kanigiri23ff9ba2014-05-13 14:42:08 +0100322
323#define MODE_RW_SHIFT 0x4
324#define MODE_RW_MASK 0x1
325#define MODE_RW_64 0x0
326#define MODE_RW_32 0x1
327
328#define MODE_EL_SHIFT 0x2
329#define MODE_EL_MASK 0x3
Achin Gupta4f6ad662013-10-25 09:08:21 +0100330#define MODE_EL3 0x3
331#define MODE_EL2 0x2
332#define MODE_EL1 0x1
333#define MODE_EL0 0x0
334
Vikram Kanigiri23ff9ba2014-05-13 14:42:08 +0100335#define MODE32_SHIFT 0
336#define MODE32_MASK 0xf
337#define MODE32_usr 0x0
338#define MODE32_fiq 0x1
339#define MODE32_irq 0x2
340#define MODE32_svc 0x3
341#define MODE32_mon 0x6
342#define MODE32_abt 0x7
343#define MODE32_hyp 0xa
344#define MODE32_und 0xb
345#define MODE32_sys 0xf
Achin Gupta4f6ad662013-10-25 09:08:21 +0100346
Vikram Kanigiri23ff9ba2014-05-13 14:42:08 +0100347#define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK)
348#define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
349#define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK)
350#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100351
Vikram Kanigiri23ff9ba2014-05-13 14:42:08 +0100352#define SPSR_64(el, sp, daif) \
353 (MODE_RW_64 << MODE_RW_SHIFT | \
354 ((el) & MODE_EL_MASK) << MODE_EL_SHIFT | \
355 ((sp) & MODE_SP_MASK) << MODE_SP_SHIFT | \
356 ((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100357
Vikram Kanigiri23ff9ba2014-05-13 14:42:08 +0100358#define SPSR_MODE32(mode, isa, endian, aif) \
359 (MODE_RW_32 << MODE_RW_SHIFT | \
360 ((mode) & MODE32_MASK) << MODE32_SHIFT | \
361 ((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \
362 ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \
363 ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)
364
Dan Handleyce4c8202015-03-30 17:15:16 +0100365/*
366 * CTR_EL0 definitions
367 */
368#define CTR_CWG_SHIFT 24
369#define CTR_CWG_MASK 0xf
370#define CTR_ERG_SHIFT 20
371#define CTR_ERG_MASK 0xf
372#define CTR_DMINLINE_SHIFT 16
373#define CTR_DMINLINE_MASK 0xf
374#define CTR_L1IP_SHIFT 14
375#define CTR_L1IP_MASK 0x3
376#define CTR_IMINLINE_SHIFT 0
377#define CTR_IMINLINE_MASK 0xf
378
379#define MAX_CACHE_LINE_SIZE 0x800 /* 2KB */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100380
Achin Guptafa9c08b2014-05-09 12:00:17 +0100381/* Physical timer control register bit fields shifts and masks */
382#define CNTP_CTL_ENABLE_SHIFT 0
383#define CNTP_CTL_IMASK_SHIFT 1
384#define CNTP_CTL_ISTATUS_SHIFT 2
385
386#define CNTP_CTL_ENABLE_MASK 1
387#define CNTP_CTL_IMASK_MASK 1
388#define CNTP_CTL_ISTATUS_MASK 1
389
390#define get_cntp_ctl_enable(x) ((x >> CNTP_CTL_ENABLE_SHIFT) & \
391 CNTP_CTL_ENABLE_MASK)
392#define get_cntp_ctl_imask(x) ((x >> CNTP_CTL_IMASK_SHIFT) & \
393 CNTP_CTL_IMASK_MASK)
394#define get_cntp_ctl_istatus(x) ((x >> CNTP_CTL_ISTATUS_SHIFT) & \
395 CNTP_CTL_ISTATUS_MASK)
396
397#define set_cntp_ctl_enable(x) (x |= 1 << CNTP_CTL_ENABLE_SHIFT)
398#define set_cntp_ctl_imask(x) (x |= 1 << CNTP_CTL_IMASK_SHIFT)
399
400#define clr_cntp_ctl_enable(x) (x &= ~(1 << CNTP_CTL_ENABLE_SHIFT))
401#define clr_cntp_ctl_imask(x) (x &= ~(1 << CNTP_CTL_IMASK_SHIFT))
402
Achin Gupta4f6ad662013-10-25 09:08:21 +0100403/* Exception Syndrome register bits and bobs */
404#define ESR_EC_SHIFT 26
405#define ESR_EC_MASK 0x3f
406#define ESR_EC_LENGTH 6
407#define EC_UNKNOWN 0x0
408#define EC_WFE_WFI 0x1
409#define EC_AARCH32_CP15_MRC_MCR 0x3
410#define EC_AARCH32_CP15_MRRC_MCRR 0x4
411#define EC_AARCH32_CP14_MRC_MCR 0x5
412#define EC_AARCH32_CP14_LDC_STC 0x6
413#define EC_FP_SIMD 0x7
414#define EC_AARCH32_CP10_MRC 0x8
415#define EC_AARCH32_CP14_MRRC_MCRR 0xc
416#define EC_ILLEGAL 0xe
417#define EC_AARCH32_SVC 0x11
418#define EC_AARCH32_HVC 0x12
419#define EC_AARCH32_SMC 0x13
420#define EC_AARCH64_SVC 0x15
421#define EC_AARCH64_HVC 0x16
422#define EC_AARCH64_SMC 0x17
423#define EC_AARCH64_SYS 0x18
424#define EC_IABORT_LOWER_EL 0x20
425#define EC_IABORT_CUR_EL 0x21
426#define EC_PC_ALIGN 0x22
427#define EC_DABORT_LOWER_EL 0x24
428#define EC_DABORT_CUR_EL 0x25
429#define EC_SP_ALIGN 0x26
430#define EC_AARCH32_FP 0x28
431#define EC_AARCH64_FP 0x2c
432#define EC_SERROR 0x2f
433
434#define EC_BITS(x) (x >> ESR_EC_SHIFT) & ESR_EC_MASK
435
Vignesh Radhakrishnana9e02602017-03-03 10:58:05 -0800436/* Reset bit inside the Reset management register for EL3 (RMR_EL3) */
437#define RMR_RESET_REQUEST_SHIFT 0x1u
438#define RMR_WARM_RESET_CPU (1u << RMR_RESET_REQUEST_SHIFT)
439
Dan Handley5f0cdb02014-05-14 17:44:19 +0100440/*******************************************************************************
Antonio Nino Diaz0b64f4e2017-02-27 17:23:54 +0000441 * Definitions of register offsets, fields and macros for CPU system
442 * instructions.
443 ******************************************************************************/
444
445#define TLBI_ADDR_SHIFT 12
446#define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF)
447#define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
448
449/*******************************************************************************
Dan Handley5f0cdb02014-05-14 17:44:19 +0100450 * Definitions of register offsets and fields in the CNTCTLBase Frame of the
451 * system level implementation of the Generic Timer.
452 ******************************************************************************/
453#define CNTNSAR 0x4
454#define CNTNSAR_NS_SHIFT(x) x
455
456#define CNTACR_BASE(x) (0x40 + (x << 2))
457#define CNTACR_RPCT_SHIFT 0x0
458#define CNTACR_RVCT_SHIFT 0x1
459#define CNTACR_RFRQ_SHIFT 0x2
460#define CNTACR_RVOFF_SHIFT 0x3
461#define CNTACR_RWVT_SHIFT 0x4
462#define CNTACR_RWPT_SHIFT 0x5
463
David Cunado495f3d32016-10-31 17:37:34 +0000464/* PMCR_EL0 definitions */
465#define PMCR_EL0_N_SHIFT 11
466#define PMCR_EL0_N_MASK 0x1f
467#define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT)
468
Achin Gupta4f6ad662013-10-25 09:08:21 +0100469#endif /* __ARCH_H__ */