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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Antonio Nino Diaz2559b2c2019-01-11 11:20:10 +00002 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-arm82cb2c12017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaz1083b2b2018-07-20 09:17:26 +01007#ifndef ARCH_H
8#define ARCH_H
Achin Gupta4f6ad662013-10-25 09:08:21 +01009
Antonio Nino Diaz09d40e02018-12-14 00:18:21 +000010#include <lib/utils_def.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010011
12/*******************************************************************************
13 * MIDR bit definitions
14 ******************************************************************************/
Varun Wadekar030567e2017-05-25 18:04:48 -070015#define MIDR_IMPL_MASK U(0xff)
16#define MIDR_IMPL_SHIFT U(0x18)
17#define MIDR_VAR_SHIFT U(20)
18#define MIDR_VAR_BITS U(4)
19#define MIDR_VAR_MASK U(0xf)
20#define MIDR_REV_SHIFT U(0)
21#define MIDR_REV_BITS U(4)
22#define MIDR_REV_MASK U(0xf)
23#define MIDR_PN_MASK U(0xfff)
24#define MIDR_PN_SHIFT U(0x4)
Achin Gupta4f6ad662013-10-25 09:08:21 +010025
26/*******************************************************************************
27 * MPIDR macros
28 ******************************************************************************/
Antonio Nino Diaz30399882018-07-12 13:23:59 +010029#define MPIDR_MT_MASK (ULL(1) << 24)
Achin Gupta4f6ad662013-10-25 09:08:21 +010030#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
Varun Wadekar030567e2017-05-25 18:04:48 -070031#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
32#define MPIDR_AFFINITY_BITS U(8)
Antonio Nino Diaz30399882018-07-12 13:23:59 +010033#define MPIDR_AFFLVL_MASK ULL(0xff)
Varun Wadekar030567e2017-05-25 18:04:48 -070034#define MPIDR_AFF0_SHIFT U(0)
35#define MPIDR_AFF1_SHIFT U(8)
36#define MPIDR_AFF2_SHIFT U(16)
37#define MPIDR_AFF3_SHIFT U(32)
Antonio Nino Diaz932b3ae2018-11-22 15:53:17 +000038#define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT
Antonio Nino Diaz30399882018-07-12 13:23:59 +010039#define MPIDR_AFFINITY_MASK ULL(0xff00ffffff)
Varun Wadekar030567e2017-05-25 18:04:48 -070040#define MPIDR_AFFLVL_SHIFT U(3)
Antonio Nino Diaz932b3ae2018-11-22 15:53:17 +000041#define MPIDR_AFFLVL0 ULL(0x0)
42#define MPIDR_AFFLVL1 ULL(0x1)
43#define MPIDR_AFFLVL2 ULL(0x2)
44#define MPIDR_AFFLVL3 ULL(0x3)
45#define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n
Vikram Kanigiri4991ecd2015-02-26 15:25:58 +000046#define MPIDR_AFFLVL0_VAL(mpidr) \
Antonio Nino Diaz0107aa42018-07-11 16:45:49 +010047 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4991ecd2015-02-26 15:25:58 +000048#define MPIDR_AFFLVL1_VAL(mpidr) \
Antonio Nino Diaz0107aa42018-07-11 16:45:49 +010049 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4991ecd2015-02-26 15:25:58 +000050#define MPIDR_AFFLVL2_VAL(mpidr) \
Antonio Nino Diaz0107aa42018-07-11 16:45:49 +010051 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4991ecd2015-02-26 15:25:58 +000052#define MPIDR_AFFLVL3_VAL(mpidr) \
Antonio Nino Diaz0107aa42018-07-11 16:45:49 +010053 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK)
Soby Mathew235585b2014-12-04 14:14:12 +000054/*
55 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
56 * add one while using this macro to define array sizes.
57 * TODO: Support only the first 3 affinity levels for now.
58 */
Varun Wadekar030567e2017-05-25 18:04:48 -070059#define MPIDR_MAX_AFFLVL U(2)
Achin Gupta4f6ad662013-10-25 09:08:21 +010060
Antonio Nino Diaz932b3ae2018-11-22 15:53:17 +000061#define MPID_MASK (MPIDR_MT_MASK | \
62 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \
63 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \
64 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \
65 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT))
66
67#define MPIDR_AFF_ID(mpid, n) \
68 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK)
69
70/*
71 * An invalid MPID. This value can be used by functions that return an MPID to
72 * indicate an error.
73 */
74#define INVALID_MPID U(0xFFFFFFFF)
Achin Gupta4f6ad662013-10-25 09:08:21 +010075
76/*******************************************************************************
Andrew Thoelke5c3272a2014-06-02 15:44:43 +010077 * Definitions for CPU system register interface to GICv3
78 ******************************************************************************/
Antonio Nino Diaz932b3ae2018-11-22 15:53:17 +000079#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
80#define ICC_SGI1R S3_0_C12_C11_5
81#define ICC_SRE_EL1 S3_0_C12_C12_5
82#define ICC_SRE_EL2 S3_4_C12_C9_5
83#define ICC_SRE_EL3 S3_6_C12_C12_5
84#define ICC_CTLR_EL1 S3_0_C12_C12_4
85#define ICC_CTLR_EL3 S3_6_C12_C12_4
86#define ICC_PMR_EL1 S3_0_C4_C6_0
87#define ICC_RPR_EL1 S3_0_C12_C11_3
88#define ICC_IGRPEN1_EL3 S3_6_c12_c12_7
89#define ICC_IGRPEN0_EL1 S3_0_c12_c12_6
90#define ICC_HPPIR0_EL1 S3_0_c12_c8_2
91#define ICC_HPPIR1_EL1 S3_0_c12_c12_2
92#define ICC_IAR0_EL1 S3_0_c12_c8_0
93#define ICC_IAR1_EL1 S3_0_c12_c12_0
94#define ICC_EOIR0_EL1 S3_0_c12_c8_1
95#define ICC_EOIR1_EL1 S3_0_c12_c12_1
96#define ICC_SGI0R_EL1 S3_0_c12_c11_7
Andrew Thoelke5c3272a2014-06-02 15:44:43 +010097
98/*******************************************************************************
Achin Guptac2b43af2013-10-31 11:27:43 +000099 * Generic timer memory mapped registers & offsets
100 ******************************************************************************/
Varun Wadekar030567e2017-05-25 18:04:48 -0700101#define CNTCR_OFF U(0x000)
Yann Gautiere1abd562019-04-17 13:47:07 +0200102#define CNTCV_OFF U(0x008)
Varun Wadekar030567e2017-05-25 18:04:48 -0700103#define CNTFID_OFF U(0x020)
Achin Guptac2b43af2013-10-31 11:27:43 +0000104
Varun Wadekar030567e2017-05-25 18:04:48 -0700105#define CNTCR_EN (U(1) << 0)
106#define CNTCR_HDBG (U(1) << 1)
Sandrine Bailleux9e864902014-03-31 11:25:18 +0100107#define CNTCR_FCREQ(x) ((x) << 8)
Achin Guptac2b43af2013-10-31 11:27:43 +0000108
109/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100110 * System register bit definitions
111 ******************************************************************************/
112/* CLIDR definitions */
Varun Wadekar030567e2017-05-25 18:04:48 -0700113#define LOUIS_SHIFT U(21)
114#define LOC_SHIFT U(24)
115#define CLIDR_FIELD_WIDTH U(3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100116
117/* CSSELR definitions */
Varun Wadekar030567e2017-05-25 18:04:48 -0700118#define LEVEL_SHIFT U(1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100119
Antonio Nino Diaz30399882018-07-12 13:23:59 +0100120/* Data cache set/way op type defines */
Varun Wadekar030567e2017-05-25 18:04:48 -0700121#define DCISW U(0x0)
122#define DCCISW U(0x1)
Ambroise Vincentbd393702019-02-21 14:16:24 +0000123#if ERRATA_A53_827319
124#define DCCSW DCCISW
125#else
Varun Wadekar030567e2017-05-25 18:04:48 -0700126#define DCCSW U(0x2)
Ambroise Vincentbd393702019-02-21 14:16:24 +0000127#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100128
129/* ID_AA64PFR0_EL1 definitions */
Varun Wadekar030567e2017-05-25 18:04:48 -0700130#define ID_AA64PFR0_EL0_SHIFT U(0)
131#define ID_AA64PFR0_EL1_SHIFT U(4)
132#define ID_AA64PFR0_EL2_SHIFT U(8)
133#define ID_AA64PFR0_EL3_SHIFT U(12)
Dimitris Papastamos380559c2017-10-12 13:02:29 +0100134#define ID_AA64PFR0_AMU_SHIFT U(44)
Antonio Nino Diaz30399882018-07-12 13:23:59 +0100135#define ID_AA64PFR0_AMU_MASK ULL(0xf)
136#define ID_AA64PFR0_ELX_MASK ULL(0xf)
Alexei Fedorove290a8fc2019-08-13 15:17:53 +0100137#define ID_AA64PFR0_GIC_SHIFT U(24)
138#define ID_AA64PFR0_GIC_WIDTH U(4)
139#define ID_AA64PFR0_GIC_MASK ULL(0xf)
David Cunado1a853372017-10-20 11:30:57 +0100140#define ID_AA64PFR0_SVE_SHIFT U(32)
Antonio Nino Diaz30399882018-07-12 13:23:59 +0100141#define ID_AA64PFR0_SVE_MASK ULL(0xf)
Jeenu Viswambharan5f835912018-07-31 16:13:33 +0100142#define ID_AA64PFR0_MPAM_SHIFT U(40)
143#define ID_AA64PFR0_MPAM_MASK ULL(0xf)
Sathees Balya65849aa2018-12-06 13:33:24 +0000144#define ID_AA64PFR0_DIT_SHIFT U(48)
145#define ID_AA64PFR0_DIT_MASK ULL(0xf)
146#define ID_AA64PFR0_DIT_LENGTH U(4)
147#define ID_AA64PFR0_DIT_SUPPORTED U(1)
Dimitris Papastamos780edd82018-01-02 15:53:01 +0000148#define ID_AA64PFR0_CSV2_SHIFT U(56)
Antonio Nino Diaz30399882018-07-12 13:23:59 +0100149#define ID_AA64PFR0_CSV2_MASK ULL(0xf)
Dimitris Papastamos780edd82018-01-02 15:53:01 +0000150#define ID_AA64PFR0_CSV2_LENGTH U(4)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100151
Alexei Fedorove290a8fc2019-08-13 15:17:53 +0100152/* Exception level handling */
Antonio Nino Diaz30399882018-07-12 13:23:59 +0100153#define EL_IMPL_NONE ULL(0)
154#define EL_IMPL_A64ONLY ULL(1)
155#define EL_IMPL_A64_A32 ULL(2)
Jeenu Viswambharanf4c8aa92017-02-21 14:40:44 +0000156
Alexei Fedorove290a8fc2019-08-13 15:17:53 +0100157/* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */
158#define ID_AA64DFR0_PMS_SHIFT U(32)
159#define ID_AA64DFR0_PMS_MASK ULL(0xf)
Achin Guptadf373732015-09-03 14:18:02 +0100160
Antonio Nino Diaz932b3ae2018-11-22 15:53:17 +0000161/* ID_AA64ISAR1_EL1 definitions */
Antonio Nino Diaz52839622019-01-31 11:58:00 +0000162#define ID_AA64ISAR1_EL1 S3_0_C0_C6_1
Antonio Nino Diaz932b3ae2018-11-22 15:53:17 +0000163#define ID_AA64ISAR1_GPI_SHIFT U(28)
Antonio Nino Diaz52839622019-01-31 11:58:00 +0000164#define ID_AA64ISAR1_GPI_MASK ULL(0xf)
Antonio Nino Diaz932b3ae2018-11-22 15:53:17 +0000165#define ID_AA64ISAR1_GPA_SHIFT U(24)
Antonio Nino Diaz52839622019-01-31 11:58:00 +0000166#define ID_AA64ISAR1_GPA_MASK ULL(0xf)
Antonio Nino Diaz932b3ae2018-11-22 15:53:17 +0000167#define ID_AA64ISAR1_API_SHIFT U(8)
Antonio Nino Diaz52839622019-01-31 11:58:00 +0000168#define ID_AA64ISAR1_API_MASK ULL(0xf)
Antonio Nino Diaz932b3ae2018-11-22 15:53:17 +0000169#define ID_AA64ISAR1_APA_SHIFT U(4)
Antonio Nino Diaz52839622019-01-31 11:58:00 +0000170#define ID_AA64ISAR1_APA_MASK ULL(0xf)
Antonio Nino Diaz932b3ae2018-11-22 15:53:17 +0000171
Antonio Nino Diaz2559b2c2019-01-11 11:20:10 +0000172/* ID_AA64MMFR0_EL1 definitions */
173#define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0)
174#define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf)
175
Varun Wadekar030567e2017-05-25 18:04:48 -0700176#define PARANGE_0000 U(32)
177#define PARANGE_0001 U(36)
178#define PARANGE_0010 U(40)
179#define PARANGE_0011 U(42)
180#define PARANGE_0100 U(44)
181#define PARANGE_0101 U(48)
Antonio Nino Diaz6504b2c2017-11-17 09:52:53 +0000182#define PARANGE_0110 U(52)
Antonio Nino Diaz00296242016-12-13 15:28:54 +0000183
Antonio Nino Diaz2fccb222017-10-24 10:07:35 +0100184#define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28)
Antonio Nino Diaz30399882018-07-12 13:23:59 +0100185#define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf)
186#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0)
187#define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf)
Antonio Nino Diaz2fccb222017-10-24 10:07:35 +0100188
189#define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24)
Antonio Nino Diaz30399882018-07-12 13:23:59 +0100190#define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf)
191#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0)
192#define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf)
Antonio Nino Diaz2fccb222017-10-24 10:07:35 +0100193
194#define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20)
Antonio Nino Diaz30399882018-07-12 13:23:59 +0100195#define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf)
196#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1)
197#define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0)
Antonio Nino Diaz2fccb222017-10-24 10:07:35 +0100198
Antonio Nino Diaz2559b2c2019-01-11 11:20:10 +0000199/* ID_AA64MMFR2_EL1 definitions */
200#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
Sathees Balyacedfa042019-01-25 11:36:01 +0000201
202#define ID_AA64MMFR2_EL1_ST_SHIFT U(28)
203#define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf)
204
Antonio Nino Diaz2559b2c2019-01-11 11:20:10 +0000205#define ID_AA64MMFR2_EL1_CNP_SHIFT U(0)
206#define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf)
207
Jeenu Viswambharan48e1d352018-11-15 11:38:03 +0000208/* ID_AA64PFR1_EL1 definitions */
209#define ID_AA64PFR1_EL1_SSBS_SHIFT U(4)
210#define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf)
211
212#define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */
213
Alexei Fedorov9fc59632019-05-24 12:17:09 +0100214#define ID_AA64PFR1_EL1_BT_SHIFT U(0)
215#define ID_AA64PFR1_EL1_BT_MASK ULL(0xf)
216
217#define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */
218
Soby Mathewb7e398d2019-07-12 09:23:38 +0100219#define ID_AA64PFR1_EL1_MTE_SHIFT U(8)
220#define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf)
221
222#define MTE_UNIMPLEMENTED ULL(0)
223#define MTE_IMPLEMENTED_EL0 ULL(1) /* MTE is only implemented at EL0 */
224#define MTE_IMPLEMENTED_ELX ULL(2) /* MTE is implemented at all ELs */
225
Achin Gupta4f6ad662013-10-25 09:08:21 +0100226/* ID_PFR1_EL1 definitions */
Varun Wadekar030567e2017-05-25 18:04:48 -0700227#define ID_PFR1_VIRTEXT_SHIFT U(12)
228#define ID_PFR1_VIRTEXT_MASK U(0xf)
Antonio Nino Diaz0107aa42018-07-11 16:45:49 +0100229#define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \
Achin Gupta4f6ad662013-10-25 09:08:21 +0100230 & ID_PFR1_VIRTEXT_MASK)
231
232/* SCTLR definitions */
David Cunado18f2efd2017-04-13 22:38:29 +0100233#define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
Varun Wadekar030567e2017-05-25 18:04:48 -0700234 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
235 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100236
David Cunado18f2efd2017-04-13 22:38:29 +0100237#define SCTLR_EL1_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
Varun Wadekar030567e2017-05-25 18:04:48 -0700238 (U(1) << 22) | (U(1) << 20) | (U(1) << 11))
Jens Wiklanderae213ce2014-09-04 10:23:27 +0200239#define SCTLR_AARCH32_EL1_RES1 \
Varun Wadekar030567e2017-05-25 18:04:48 -0700240 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \
241 (U(1) << 4) | (U(1) << 3))
Jens Wiklanderae213ce2014-09-04 10:23:27 +0200242
David Cunado18f2efd2017-04-13 22:38:29 +0100243#define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
244 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
245 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
246
Jeenu Viswambharan48e1d352018-11-15 11:38:03 +0000247#define SCTLR_M_BIT (ULL(1) << 0)
248#define SCTLR_A_BIT (ULL(1) << 1)
249#define SCTLR_C_BIT (ULL(1) << 2)
250#define SCTLR_SA_BIT (ULL(1) << 3)
251#define SCTLR_SA0_BIT (ULL(1) << 4)
252#define SCTLR_CP15BEN_BIT (ULL(1) << 5)
253#define SCTLR_ITD_BIT (ULL(1) << 7)
254#define SCTLR_SED_BIT (ULL(1) << 8)
255#define SCTLR_UMA_BIT (ULL(1) << 9)
256#define SCTLR_I_BIT (ULL(1) << 12)
Alexei Fedorovc4655152019-07-10 10:49:12 +0100257#define SCTLR_EnDB_BIT (ULL(1) << 13)
Jeenu Viswambharan48e1d352018-11-15 11:38:03 +0000258#define SCTLR_DZE_BIT (ULL(1) << 14)
259#define SCTLR_UCT_BIT (ULL(1) << 15)
260#define SCTLR_NTWI_BIT (ULL(1) << 16)
261#define SCTLR_NTWE_BIT (ULL(1) << 18)
262#define SCTLR_WXN_BIT (ULL(1) << 19)
263#define SCTLR_UWXN_BIT (ULL(1) << 20)
Louis Mayencourt5f5d1ed2019-02-20 12:11:41 +0000264#define SCTLR_IESB_BIT (ULL(1) << 21)
Jeenu Viswambharan48e1d352018-11-15 11:38:03 +0000265#define SCTLR_E0E_BIT (ULL(1) << 24)
266#define SCTLR_EE_BIT (ULL(1) << 25)
267#define SCTLR_UCI_BIT (ULL(1) << 26)
Alexei Fedorovc4655152019-07-10 10:49:12 +0100268#define SCTLR_EnDA_BIT (ULL(1) << 27)
269#define SCTLR_EnIB_BIT (ULL(1) << 30)
Antonio Nino Diaz52839622019-01-31 11:58:00 +0000270#define SCTLR_EnIA_BIT (ULL(1) << 31)
Alexei Fedorov9fc59632019-05-24 12:17:09 +0100271#define SCTLR_BT0_BIT (ULL(1) << 35)
272#define SCTLR_BT1_BIT (ULL(1) << 36)
273#define SCTLR_BT_BIT (ULL(1) << 36)
Jeenu Viswambharan48e1d352018-11-15 11:38:03 +0000274#define SCTLR_DSSBS_BIT (ULL(1) << 44)
David Cunado18f2efd2017-04-13 22:38:29 +0100275#define SCTLR_RESET_VAL SCTLR_EL3_RES1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100276
Achin Gupta4f6ad662013-10-25 09:08:21 +0100277/* CPACR_El1 definitions */
Varun Wadekar030567e2017-05-25 18:04:48 -0700278#define CPACR_EL1_FPEN(x) ((x) << 20)
279#define CPACR_EL1_FP_TRAP_EL0 U(0x1)
280#define CPACR_EL1_FP_TRAP_ALL U(0x2)
281#define CPACR_EL1_FP_TRAP_NONE U(0x3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100282
283/* SCR definitions */
Varun Wadekar030567e2017-05-25 18:04:48 -0700284#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
Soby Mathewb7e398d2019-07-12 09:23:38 +0100285#define SCR_ATA_BIT (U(1) << 26)
Jeenu Viswambharan1a7c1cf2017-12-08 12:13:51 +0000286#define SCR_FIEN_BIT (U(1) << 21)
Jeenu Viswambharan3ff4aaa2018-08-15 14:29:29 +0100287#define SCR_API_BIT (U(1) << 17)
288#define SCR_APK_BIT (U(1) << 16)
Varun Wadekar030567e2017-05-25 18:04:48 -0700289#define SCR_TWE_BIT (U(1) << 13)
290#define SCR_TWI_BIT (U(1) << 12)
291#define SCR_ST_BIT (U(1) << 11)
292#define SCR_RW_BIT (U(1) << 10)
293#define SCR_SIF_BIT (U(1) << 9)
294#define SCR_HCE_BIT (U(1) << 8)
295#define SCR_SMD_BIT (U(1) << 7)
296#define SCR_EA_BIT (U(1) << 3)
297#define SCR_FIQ_BIT (U(1) << 2)
298#define SCR_IRQ_BIT (U(1) << 1)
299#define SCR_NS_BIT (U(1) << 0)
300#define SCR_VALID_BIT_MASK U(0x2f8f)
David Cunado18f2efd2017-04-13 22:38:29 +0100301#define SCR_RESET_VAL SCR_RES1_BITS
Achin Gupta4f6ad662013-10-25 09:08:21 +0100302
David Cunado18f2efd2017-04-13 22:38:29 +0100303/* MDCR_EL3 definitions */
Alexei Fedorove290a8fc2019-08-13 15:17:53 +0100304#define MDCR_SCCD_BIT (ULL(1) << 23)
305#define MDCR_SPME_BIT (ULL(1) << 17)
306#define MDCR_SDD_BIT (ULL(1) << 16)
dp-arm85e93ba2017-02-08 11:51:50 +0000307#define MDCR_SPD32(x) ((x) << 14)
Antonio Nino Diazed4fc6f2019-02-18 16:55:43 +0000308#define MDCR_SPD32_LEGACY ULL(0x0)
309#define MDCR_SPD32_DISABLE ULL(0x2)
310#define MDCR_SPD32_ENABLE ULL(0x3)
dp-armd832aee2017-05-23 09:32:49 +0100311#define MDCR_NSPB(x) ((x) << 12)
Antonio Nino Diazed4fc6f2019-02-18 16:55:43 +0000312#define MDCR_NSPB_EL1 ULL(0x3)
313#define MDCR_TDOSA_BIT (ULL(1) << 10)
314#define MDCR_TDA_BIT (ULL(1) << 9)
315#define MDCR_TPM_BIT (ULL(1) << 6)
Antonio Nino Diazed4fc6f2019-02-18 16:55:43 +0000316#define MDCR_EL3_RESET_VAL ULL(0x0)
dp-arm85e93ba2017-02-08 11:51:50 +0000317
David Cunado18f2efd2017-04-13 22:38:29 +0100318/* MDCR_EL2 definitions */
Alexei Fedorove290a8fc2019-08-13 15:17:53 +0100319#define MDCR_EL2_HLP (U(1) << 26)
320#define MDCR_EL2_HCCD (U(1) << 23)
321#define MDCR_EL2_TTRF (U(1) << 19)
322#define MDCR_EL2_HPMD (U(1) << 17)
dp-armd832aee2017-05-23 09:32:49 +0100323#define MDCR_EL2_TPMS (U(1) << 14)
324#define MDCR_EL2_E2PB(x) ((x) << 12)
325#define MDCR_EL2_E2PB_EL1 U(0x3)
David Cunado18f2efd2017-04-13 22:38:29 +0100326#define MDCR_EL2_TDRA_BIT (U(1) << 11)
327#define MDCR_EL2_TDOSA_BIT (U(1) << 10)
328#define MDCR_EL2_TDA_BIT (U(1) << 9)
329#define MDCR_EL2_TDE_BIT (U(1) << 8)
330#define MDCR_EL2_HPME_BIT (U(1) << 7)
331#define MDCR_EL2_TPM_BIT (U(1) << 6)
332#define MDCR_EL2_TPMCR_BIT (U(1) << 5)
333#define MDCR_EL2_RESET_VAL U(0x0)
334
335/* HSTR_EL2 definitions */
336#define HSTR_EL2_RESET_VAL U(0x0)
337#define HSTR_EL2_T_MASK U(0xff)
338
339/* CNTHP_CTL_EL2 definitions */
340#define CNTHP_CTL_ENABLE_BIT (U(1) << 0)
341#define CNTHP_CTL_RESET_VAL U(0x0)
342
343/* VTTBR_EL2 definitions */
344#define VTTBR_RESET_VAL ULL(0x0)
345#define VTTBR_VMID_MASK ULL(0xff)
346#define VTTBR_VMID_SHIFT U(48)
347#define VTTBR_BADDR_MASK ULL(0xffffffffffff)
348#define VTTBR_BADDR_SHIFT U(0)
dp-arm85e93ba2017-02-08 11:51:50 +0000349
Achin Gupta4f6ad662013-10-25 09:08:21 +0100350/* HCR definitions */
Jeenu Viswambharan3ff4aaa2018-08-15 14:29:29 +0100351#define HCR_API_BIT (ULL(1) << 41)
352#define HCR_APK_BIT (ULL(1) << 40)
Antonio Nino Diaz932b3ae2018-11-22 15:53:17 +0000353#define HCR_TGE_BIT (ULL(1) << 27)
Varun Wadekar030567e2017-05-25 18:04:48 -0700354#define HCR_RW_SHIFT U(31)
355#define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT)
Antonio Nino Diaz30399882018-07-12 13:23:59 +0100356#define HCR_AMO_BIT (ULL(1) << 5)
357#define HCR_IMO_BIT (ULL(1) << 4)
358#define HCR_FMO_BIT (ULL(1) << 3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100359
Gerald Lejeune6b836cf2016-03-22 11:11:46 +0100360/* ISR definitions */
Varun Wadekar030567e2017-05-25 18:04:48 -0700361#define ISR_A_SHIFT U(8)
362#define ISR_I_SHIFT U(7)
363#define ISR_F_SHIFT U(6)
Gerald Lejeune6b836cf2016-03-22 11:11:46 +0100364
Achin Gupta4f6ad662013-10-25 09:08:21 +0100365/* CNTHCTL_EL2 definitions */
David Cunado18f2efd2017-04-13 22:38:29 +0100366#define CNTHCTL_RESET_VAL U(0x0)
Varun Wadekar030567e2017-05-25 18:04:48 -0700367#define EVNTEN_BIT (U(1) << 2)
368#define EL1PCEN_BIT (U(1) << 1)
369#define EL1PCTEN_BIT (U(1) << 0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100370
371/* CNTKCTL_EL1 definitions */
Varun Wadekar030567e2017-05-25 18:04:48 -0700372#define EL0PTEN_BIT (U(1) << 9)
373#define EL0VTEN_BIT (U(1) << 8)
374#define EL0PCTEN_BIT (U(1) << 0)
375#define EL0VCTEN_BIT (U(1) << 1)
376#define EVNTEN_BIT (U(1) << 2)
377#define EVNTDIR_BIT (U(1) << 3)
378#define EVNTI_SHIFT U(4)
379#define EVNTI_MASK U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100380
381/* CPTR_EL3 definitions */
Varun Wadekar030567e2017-05-25 18:04:48 -0700382#define TCPAC_BIT (U(1) << 31)
Dimitris Papastamos380559c2017-10-12 13:02:29 +0100383#define TAM_BIT (U(1) << 30)
Varun Wadekar030567e2017-05-25 18:04:48 -0700384#define TTA_BIT (U(1) << 20)
385#define TFP_BIT (U(1) << 10)
David Cunado1a853372017-10-20 11:30:57 +0100386#define CPTR_EZ_BIT (U(1) << 8)
David Cunado18f2efd2017-04-13 22:38:29 +0100387#define CPTR_EL3_RESET_VAL U(0x0)
388
389/* CPTR_EL2 definitions */
390#define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff)))
391#define CPTR_EL2_TCPAC_BIT (U(1) << 31)
Dimitris Papastamos380559c2017-10-12 13:02:29 +0100392#define CPTR_EL2_TAM_BIT (U(1) << 30)
David Cunado18f2efd2017-04-13 22:38:29 +0100393#define CPTR_EL2_TTA_BIT (U(1) << 20)
394#define CPTR_EL2_TFP_BIT (U(1) << 10)
David Cunado1a853372017-10-20 11:30:57 +0100395#define CPTR_EL2_TZ_BIT (U(1) << 8)
David Cunado18f2efd2017-04-13 22:38:29 +0100396#define CPTR_EL2_RESET_VAL CPTR_EL2_RES1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100397
398/* CPSR/SPSR definitions */
Varun Wadekar030567e2017-05-25 18:04:48 -0700399#define DAIF_FIQ_BIT (U(1) << 0)
400#define DAIF_IRQ_BIT (U(1) << 1)
401#define DAIF_ABT_BIT (U(1) << 2)
402#define DAIF_DBG_BIT (U(1) << 3)
403#define SPSR_DAIF_SHIFT U(6)
404#define SPSR_DAIF_MASK U(0xf)
Vikram Kanigiri23ff9ba2014-05-13 14:42:08 +0100405
Varun Wadekar030567e2017-05-25 18:04:48 -0700406#define SPSR_AIF_SHIFT U(6)
407#define SPSR_AIF_MASK U(0x7)
Vikram Kanigiri23ff9ba2014-05-13 14:42:08 +0100408
Varun Wadekar030567e2017-05-25 18:04:48 -0700409#define SPSR_E_SHIFT U(9)
410#define SPSR_E_MASK U(0x1)
411#define SPSR_E_LITTLE U(0x0)
412#define SPSR_E_BIG U(0x1)
Vikram Kanigiri23ff9ba2014-05-13 14:42:08 +0100413
Varun Wadekar030567e2017-05-25 18:04:48 -0700414#define SPSR_T_SHIFT U(5)
415#define SPSR_T_MASK U(0x1)
416#define SPSR_T_ARM U(0x0)
417#define SPSR_T_THUMB U(0x1)
Vikram Kanigiri23ff9ba2014-05-13 14:42:08 +0100418
Dimitris Papastamosa1781a22017-12-18 13:46:21 +0000419#define SPSR_M_SHIFT U(4)
420#define SPSR_M_MASK U(0x1)
421#define SPSR_M_AARCH64 U(0x0)
422#define SPSR_M_AARCH32 U(0x1)
423
John Tsichritzisc250cc32019-07-23 11:12:41 +0100424#define SPSR_SSBS_BIT_AARCH64 BIT_64(12)
425#define SPSR_SSBS_BIT_AARCH32 BIT_64(23)
426
Vikram Kanigiri23ff9ba2014-05-13 14:42:08 +0100427#define DISABLE_ALL_EXCEPTIONS \
428 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
429
Antonio Nino Diaz932b3ae2018-11-22 15:53:17 +0000430#define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT)
431
Yatharth Kochar07570d52016-11-14 12:01:04 +0000432/*
433 * RMR_EL3 definitions
434 */
Varun Wadekar030567e2017-05-25 18:04:48 -0700435#define RMR_EL3_RR_BIT (U(1) << 1)
436#define RMR_EL3_AA64_BIT (U(1) << 0)
Yatharth Kochar07570d52016-11-14 12:01:04 +0000437
438/*
439 * HI-VECTOR address for AArch32 state
440 */
Antonio Nino Diaz932b3ae2018-11-22 15:53:17 +0000441#define HI_VECTOR_BASE U(0xFFFF0000)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100442
443/*
444 * TCR defintions
445 */
Antonio Nino Diaz932b3ae2018-11-22 15:53:17 +0000446#define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
Antonio Nino Diaz1a92a0e2018-08-07 19:59:49 +0100447#define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
Varun Wadekar030567e2017-05-25 18:04:48 -0700448#define TCR_EL1_IPS_SHIFT U(32)
Antonio Nino Diaz1a92a0e2018-08-07 19:59:49 +0100449#define TCR_EL2_PS_SHIFT U(16)
Varun Wadekar030567e2017-05-25 18:04:48 -0700450#define TCR_EL3_PS_SHIFT U(16)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100451
Antonio Nino Diaz30399882018-07-12 13:23:59 +0100452#define TCR_TxSZ_MIN ULL(16)
453#define TCR_TxSZ_MAX ULL(39)
Sathees Balyacedfa042019-01-25 11:36:01 +0000454#define TCR_TxSZ_MAX_TTST ULL(48)
Antonio Nino Diaze8719552016-08-02 09:21:41 +0100455
Antonio Nino Diaz6de69652019-03-27 11:10:31 +0000456#define TCR_T0SZ_SHIFT U(0)
457#define TCR_T1SZ_SHIFT U(16)
458
Lin Ma73ad2572014-06-27 16:56:30 -0700459/* (internal) physical address size bits in EL3/EL1 */
Antonio Nino Diaz30399882018-07-12 13:23:59 +0100460#define TCR_PS_BITS_4GB ULL(0x0)
461#define TCR_PS_BITS_64GB ULL(0x1)
462#define TCR_PS_BITS_1TB ULL(0x2)
463#define TCR_PS_BITS_4TB ULL(0x3)
464#define TCR_PS_BITS_16TB ULL(0x4)
465#define TCR_PS_BITS_256TB ULL(0x5)
Lin Ma73ad2572014-06-27 16:56:30 -0700466
Varun Wadekar030567e2017-05-25 18:04:48 -0700467#define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000)
468#define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000)
469#define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000)
470#define ADDR_MASK_40_TO_41 ULL(0x0000030000000000)
471#define ADDR_MASK_36_TO_39 ULL(0x000000F000000000)
472#define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100473
Antonio Nino Diaz30399882018-07-12 13:23:59 +0100474#define TCR_RGN_INNER_NC (ULL(0x0) << 8)
475#define TCR_RGN_INNER_WBA (ULL(0x1) << 8)
476#define TCR_RGN_INNER_WT (ULL(0x2) << 8)
477#define TCR_RGN_INNER_WBNA (ULL(0x3) << 8)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100478
Antonio Nino Diaz30399882018-07-12 13:23:59 +0100479#define TCR_RGN_OUTER_NC (ULL(0x0) << 10)
480#define TCR_RGN_OUTER_WBA (ULL(0x1) << 10)
481#define TCR_RGN_OUTER_WT (ULL(0x2) << 10)
482#define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100483
Antonio Nino Diaz30399882018-07-12 13:23:59 +0100484#define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12)
485#define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12)
486#define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100487
Antonio Nino Diaz6de69652019-03-27 11:10:31 +0000488#define TCR_RGN1_INNER_NC (ULL(0x0) << 24)
489#define TCR_RGN1_INNER_WBA (ULL(0x1) << 24)
490#define TCR_RGN1_INNER_WT (ULL(0x2) << 24)
491#define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24)
492
493#define TCR_RGN1_OUTER_NC (ULL(0x0) << 26)
494#define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26)
495#define TCR_RGN1_OUTER_WT (ULL(0x2) << 26)
496#define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26)
497
498#define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28)
499#define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28)
500#define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28)
501
Antonio Nino Diaz2fccb222017-10-24 10:07:35 +0100502#define TCR_TG0_SHIFT U(14)
Antonio Nino Diaz30399882018-07-12 13:23:59 +0100503#define TCR_TG0_MASK ULL(3)
Antonio Nino Diaz2fccb222017-10-24 10:07:35 +0100504#define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT)
505#define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT)
506#define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT)
507
Antonio Nino Diaz6de69652019-03-27 11:10:31 +0000508#define TCR_TG1_SHIFT U(30)
509#define TCR_TG1_MASK ULL(3)
510#define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT)
511#define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT)
512#define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT)
513
Antonio Nino Diaz30399882018-07-12 13:23:59 +0100514#define TCR_EPD0_BIT (ULL(1) << 7)
515#define TCR_EPD1_BIT (ULL(1) << 23)
Antonio Nino Diaz3388b382017-09-15 10:30:34 +0100516
Varun Wadekar030567e2017-05-25 18:04:48 -0700517#define MODE_SP_SHIFT U(0x0)
518#define MODE_SP_MASK U(0x1)
519#define MODE_SP_EL0 U(0x0)
520#define MODE_SP_ELX U(0x1)
Vikram Kanigiri23ff9ba2014-05-13 14:42:08 +0100521
Varun Wadekar030567e2017-05-25 18:04:48 -0700522#define MODE_RW_SHIFT U(0x4)
523#define MODE_RW_MASK U(0x1)
524#define MODE_RW_64 U(0x0)
525#define MODE_RW_32 U(0x1)
Vikram Kanigiri23ff9ba2014-05-13 14:42:08 +0100526
Varun Wadekar030567e2017-05-25 18:04:48 -0700527#define MODE_EL_SHIFT U(0x2)
528#define MODE_EL_MASK U(0x3)
529#define MODE_EL3 U(0x3)
530#define MODE_EL2 U(0x2)
531#define MODE_EL1 U(0x1)
532#define MODE_EL0 U(0x0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100533
Varun Wadekar030567e2017-05-25 18:04:48 -0700534#define MODE32_SHIFT U(0)
535#define MODE32_MASK U(0xf)
536#define MODE32_usr U(0x0)
537#define MODE32_fiq U(0x1)
538#define MODE32_irq U(0x2)
539#define MODE32_svc U(0x3)
540#define MODE32_mon U(0x6)
541#define MODE32_abt U(0x7)
542#define MODE32_hyp U(0xa)
543#define MODE32_und U(0xb)
544#define MODE32_sys U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100545
Vikram Kanigiri23ff9ba2014-05-13 14:42:08 +0100546#define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK)
547#define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
548#define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK)
549#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100550
John Tsichritzisc250cc32019-07-23 11:12:41 +0100551#define SPSR_64(el, sp, daif) \
552 (((MODE_RW_64 << MODE_RW_SHIFT) | \
553 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \
554 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \
555 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \
556 (~(SPSR_SSBS_BIT_AARCH64)))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100557
Vikram Kanigiri23ff9ba2014-05-13 14:42:08 +0100558#define SPSR_MODE32(mode, isa, endian, aif) \
John Tsichritzisc250cc32019-07-23 11:12:41 +0100559 (((MODE_RW_32 << MODE_RW_SHIFT) | \
Varun Wadekar030567e2017-05-25 18:04:48 -0700560 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \
561 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \
562 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \
John Tsichritzisc250cc32019-07-23 11:12:41 +0100563 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \
564 (~(SPSR_SSBS_BIT_AARCH32)))
Vikram Kanigiri23ff9ba2014-05-13 14:42:08 +0100565
Dan Handleyce4c8202015-03-30 17:15:16 +0100566/*
Isla Mitchell9fce2722017-08-07 11:20:13 +0100567 * TTBR Definitions
568 */
Antonio Nino Diaz30399882018-07-12 13:23:59 +0100569#define TTBR_CNP_BIT ULL(0x1)
Isla Mitchell9fce2722017-08-07 11:20:13 +0100570
571/*
Dan Handleyce4c8202015-03-30 17:15:16 +0100572 * CTR_EL0 definitions
573 */
Varun Wadekar030567e2017-05-25 18:04:48 -0700574#define CTR_CWG_SHIFT U(24)
575#define CTR_CWG_MASK U(0xf)
576#define CTR_ERG_SHIFT U(20)
577#define CTR_ERG_MASK U(0xf)
578#define CTR_DMINLINE_SHIFT U(16)
579#define CTR_DMINLINE_MASK U(0xf)
580#define CTR_L1IP_SHIFT U(14)
581#define CTR_L1IP_MASK U(0x3)
582#define CTR_IMINLINE_SHIFT U(0)
583#define CTR_IMINLINE_MASK U(0xf)
Dan Handleyce4c8202015-03-30 17:15:16 +0100584
Varun Wadekar030567e2017-05-25 18:04:48 -0700585#define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100586
Achin Guptafa9c08b2014-05-09 12:00:17 +0100587/* Physical timer control register bit fields shifts and masks */
Varun Wadekar030567e2017-05-25 18:04:48 -0700588#define CNTP_CTL_ENABLE_SHIFT U(0)
589#define CNTP_CTL_IMASK_SHIFT U(1)
590#define CNTP_CTL_ISTATUS_SHIFT U(2)
Achin Guptafa9c08b2014-05-09 12:00:17 +0100591
Varun Wadekar030567e2017-05-25 18:04:48 -0700592#define CNTP_CTL_ENABLE_MASK U(1)
593#define CNTP_CTL_IMASK_MASK U(1)
594#define CNTP_CTL_ISTATUS_MASK U(1)
Achin Guptafa9c08b2014-05-09 12:00:17 +0100595
Achin Gupta4f6ad662013-10-25 09:08:21 +0100596/* Exception Syndrome register bits and bobs */
Varun Wadekar030567e2017-05-25 18:04:48 -0700597#define ESR_EC_SHIFT U(26)
598#define ESR_EC_MASK U(0x3f)
599#define ESR_EC_LENGTH U(6)
600#define EC_UNKNOWN U(0x0)
601#define EC_WFE_WFI U(0x1)
602#define EC_AARCH32_CP15_MRC_MCR U(0x3)
603#define EC_AARCH32_CP15_MRRC_MCRR U(0x4)
604#define EC_AARCH32_CP14_MRC_MCR U(0x5)
605#define EC_AARCH32_CP14_LDC_STC U(0x6)
606#define EC_FP_SIMD U(0x7)
607#define EC_AARCH32_CP10_MRC U(0x8)
608#define EC_AARCH32_CP14_MRRC_MCRR U(0xc)
609#define EC_ILLEGAL U(0xe)
610#define EC_AARCH32_SVC U(0x11)
611#define EC_AARCH32_HVC U(0x12)
612#define EC_AARCH32_SMC U(0x13)
613#define EC_AARCH64_SVC U(0x15)
614#define EC_AARCH64_HVC U(0x16)
615#define EC_AARCH64_SMC U(0x17)
616#define EC_AARCH64_SYS U(0x18)
617#define EC_IABORT_LOWER_EL U(0x20)
618#define EC_IABORT_CUR_EL U(0x21)
619#define EC_PC_ALIGN U(0x22)
620#define EC_DABORT_LOWER_EL U(0x24)
621#define EC_DABORT_CUR_EL U(0x25)
622#define EC_SP_ALIGN U(0x26)
623#define EC_AARCH32_FP U(0x28)
624#define EC_AARCH64_FP U(0x2c)
625#define EC_SERROR U(0x2f)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100626
Jeenu Viswambharan76454ab2017-11-30 12:54:15 +0000627/*
628 * External Abort bit in Instruction and Data Aborts synchronous exception
629 * syndromes.
630 */
631#define ESR_ISS_EABORT_EA_BIT U(9)
632
Varun Wadekar030567e2017-05-25 18:04:48 -0700633#define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100634
Vignesh Radhakrishnana9e02602017-03-03 10:58:05 -0800635/* Reset bit inside the Reset management register for EL3 (RMR_EL3) */
Varun Wadekar030567e2017-05-25 18:04:48 -0700636#define RMR_RESET_REQUEST_SHIFT U(0x1)
637#define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT)
Vignesh Radhakrishnana9e02602017-03-03 10:58:05 -0800638
Dan Handley5f0cdb02014-05-14 17:44:19 +0100639/*******************************************************************************
Antonio Nino Diaz0b64f4e2017-02-27 17:23:54 +0000640 * Definitions of register offsets, fields and macros for CPU system
641 * instructions.
642 ******************************************************************************/
643
Varun Wadekar030567e2017-05-25 18:04:48 -0700644#define TLBI_ADDR_SHIFT U(12)
Antonio Nino Diaz0b64f4e2017-02-27 17:23:54 +0000645#define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF)
646#define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
647
648/*******************************************************************************
Dan Handley5f0cdb02014-05-14 17:44:19 +0100649 * Definitions of register offsets and fields in the CNTCTLBase Frame of the
650 * system level implementation of the Generic Timer.
651 ******************************************************************************/
Soby Mathew342d6222018-06-11 16:21:30 +0100652#define CNTCTLBASE_CNTFRQ U(0x0)
Varun Wadekar030567e2017-05-25 18:04:48 -0700653#define CNTNSAR U(0x4)
654#define CNTNSAR_NS_SHIFT(x) (x)
Dan Handley5f0cdb02014-05-14 17:44:19 +0100655
Varun Wadekar030567e2017-05-25 18:04:48 -0700656#define CNTACR_BASE(x) (U(0x40) + ((x) << 2))
657#define CNTACR_RPCT_SHIFT U(0x0)
658#define CNTACR_RVCT_SHIFT U(0x1)
659#define CNTACR_RFRQ_SHIFT U(0x2)
660#define CNTACR_RVOFF_SHIFT U(0x3)
661#define CNTACR_RWVT_SHIFT U(0x4)
662#define CNTACR_RWPT_SHIFT U(0x5)
Dan Handley5f0cdb02014-05-14 17:44:19 +0100663
Soby Mathew342d6222018-06-11 16:21:30 +0100664/*******************************************************************************
Antonio Nino Diaz932b3ae2018-11-22 15:53:17 +0000665 * Definitions of register offsets and fields in the CNTBaseN Frame of the
Soby Mathew342d6222018-06-11 16:21:30 +0100666 * system level implementation of the Generic Timer.
667 ******************************************************************************/
Antonio Nino Diaz932b3ae2018-11-22 15:53:17 +0000668/* Physical Count register. */
669#define CNTPCT_LO U(0x0)
670/* Counter Frequency register. */
671#define CNTBASEN_CNTFRQ U(0x10)
672/* Physical Timer CompareValue register. */
673#define CNTP_CVAL_LO U(0x20)
674/* Physical Timer Control register. */
675#define CNTP_CTL U(0x2c)
Soby Mathew342d6222018-06-11 16:21:30 +0100676
David Cunado495f3d32016-10-31 17:37:34 +0000677/* PMCR_EL0 definitions */
David Cunado3e61b2b2017-10-02 17:41:39 +0100678#define PMCR_EL0_RESET_VAL U(0x0)
Varun Wadekar030567e2017-05-25 18:04:48 -0700679#define PMCR_EL0_N_SHIFT U(11)
680#define PMCR_EL0_N_MASK U(0x1f)
David Cunado495f3d32016-10-31 17:37:34 +0000681#define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT)
Alexei Fedorove290a8fc2019-08-13 15:17:53 +0100682#define PMCR_EL0_LP_BIT (U(1) << 7)
David Cunado3e61b2b2017-10-02 17:41:39 +0100683#define PMCR_EL0_LC_BIT (U(1) << 6)
684#define PMCR_EL0_DP_BIT (U(1) << 5)
685#define PMCR_EL0_X_BIT (U(1) << 4)
686#define PMCR_EL0_D_BIT (U(1) << 3)
Alexei Fedorove290a8fc2019-08-13 15:17:53 +0100687#define PMCR_EL0_C_BIT (U(1) << 2)
688#define PMCR_EL0_P_BIT (U(1) << 1)
689#define PMCR_EL0_E_BIT (U(1) << 0)
David Cunado495f3d32016-10-31 17:37:34 +0000690
Isla Mitchell04880e32017-07-21 14:44:36 +0100691/*******************************************************************************
David Cunado1a853372017-10-20 11:30:57 +0100692 * Definitions for system register interface to SVE
693 ******************************************************************************/
694#define ZCR_EL3 S3_6_C1_C2_0
695#define ZCR_EL2 S3_4_C1_C2_0
696
697/* ZCR_EL3 definitions */
698#define ZCR_EL3_LEN_MASK U(0xf)
699
700/* ZCR_EL2 definitions */
701#define ZCR_EL2_LEN_MASK U(0xf)
702
703/*******************************************************************************
Isla Mitchell04880e32017-07-21 14:44:36 +0100704 * Definitions of MAIR encodings for device and normal memory
705 ******************************************************************************/
706/*
707 * MAIR encodings for device memory attributes.
708 */
709#define MAIR_DEV_nGnRnE ULL(0x0)
710#define MAIR_DEV_nGnRE ULL(0x4)
711#define MAIR_DEV_nGRE ULL(0x8)
712#define MAIR_DEV_GRE ULL(0xc)
713
714/*
715 * MAIR encodings for normal memory attributes.
716 *
717 * Cache Policy
718 * WT: Write Through
719 * WB: Write Back
720 * NC: Non-Cacheable
721 *
722 * Transient Hint
723 * NTR: Non-Transient
724 * TR: Transient
725 *
726 * Allocation Policy
727 * RA: Read Allocate
728 * WA: Write Allocate
729 * RWA: Read and Write Allocate
730 * NA: No Allocation
731 */
732#define MAIR_NORM_WT_TR_WA ULL(0x1)
733#define MAIR_NORM_WT_TR_RA ULL(0x2)
734#define MAIR_NORM_WT_TR_RWA ULL(0x3)
735#define MAIR_NORM_NC ULL(0x4)
736#define MAIR_NORM_WB_TR_WA ULL(0x5)
737#define MAIR_NORM_WB_TR_RA ULL(0x6)
738#define MAIR_NORM_WB_TR_RWA ULL(0x7)
739#define MAIR_NORM_WT_NTR_NA ULL(0x8)
740#define MAIR_NORM_WT_NTR_WA ULL(0x9)
741#define MAIR_NORM_WT_NTR_RA ULL(0xa)
742#define MAIR_NORM_WT_NTR_RWA ULL(0xb)
743#define MAIR_NORM_WB_NTR_NA ULL(0xc)
744#define MAIR_NORM_WB_NTR_WA ULL(0xd)
745#define MAIR_NORM_WB_NTR_RA ULL(0xe)
746#define MAIR_NORM_WB_NTR_RWA ULL(0xf)
747
Antonio Nino Diaz30399882018-07-12 13:23:59 +0100748#define MAIR_NORM_OUTER_SHIFT U(4)
Isla Mitchell04880e32017-07-21 14:44:36 +0100749
Antonio Nino Diaz30399882018-07-12 13:23:59 +0100750#define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \
751 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
Isla Mitchell04880e32017-07-21 14:44:36 +0100752
Jeenu Viswambharan781f4aa2017-10-19 09:15:15 +0100753/* PAR_EL1 fields */
Antonio Nino Diaz30399882018-07-12 13:23:59 +0100754#define PAR_F_SHIFT U(0)
755#define PAR_F_MASK ULL(0x1)
756#define PAR_ADDR_SHIFT U(12)
757#define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */
Jeenu Viswambharan781f4aa2017-10-19 09:15:15 +0100758
Dimitris Papastamos281a08c2017-10-13 12:06:06 +0100759/*******************************************************************************
760 * Definitions for system register interface to SPE
761 ******************************************************************************/
762#define PMBLIMITR_EL1 S3_0_C9_C10_0
763
Dimitris Papastamos380559c2017-10-12 13:02:29 +0100764/*******************************************************************************
Jeenu Viswambharan5f835912018-07-31 16:13:33 +0100765 * Definitions for system register interface to MPAM
766 ******************************************************************************/
767#define MPAMIDR_EL1 S3_0_C10_C4_4
768#define MPAM2_EL2 S3_4_C10_C5_0
769#define MPAMHCR_EL2 S3_4_C10_C4_0
770#define MPAM3_EL3 S3_6_C10_C5_0
771
772/*******************************************************************************
Dimitris Papastamos380559c2017-10-12 13:02:29 +0100773 * Definitions for system register interface to AMU for ARMv8.4 onwards
774 ******************************************************************************/
775#define AMCR_EL0 S3_3_C13_C2_0
776#define AMCFGR_EL0 S3_3_C13_C2_1
777#define AMCGCR_EL0 S3_3_C13_C2_2
778#define AMUSERENR_EL0 S3_3_C13_C2_3
779#define AMCNTENCLR0_EL0 S3_3_C13_C2_4
780#define AMCNTENSET0_EL0 S3_3_C13_C2_5
781#define AMCNTENCLR1_EL0 S3_3_C13_C3_0
782#define AMCNTENSET1_EL0 S3_3_C13_C3_1
783
784/* Activity Monitor Group 0 Event Counter Registers */
785#define AMEVCNTR00_EL0 S3_3_C13_C4_0
786#define AMEVCNTR01_EL0 S3_3_C13_C4_1
787#define AMEVCNTR02_EL0 S3_3_C13_C4_2
788#define AMEVCNTR03_EL0 S3_3_C13_C4_3
789
790/* Activity Monitor Group 0 Event Type Registers */
791#define AMEVTYPER00_EL0 S3_3_C13_C6_0
792#define AMEVTYPER01_EL0 S3_3_C13_C6_1
793#define AMEVTYPER02_EL0 S3_3_C13_C6_2
794#define AMEVTYPER03_EL0 S3_3_C13_C6_3
795
Dimitris Papastamos0767d502017-11-13 09:49:45 +0000796/* Activity Monitor Group 1 Event Counter Registers */
797#define AMEVCNTR10_EL0 S3_3_C13_C12_0
798#define AMEVCNTR11_EL0 S3_3_C13_C12_1
799#define AMEVCNTR12_EL0 S3_3_C13_C12_2
800#define AMEVCNTR13_EL0 S3_3_C13_C12_3
801#define AMEVCNTR14_EL0 S3_3_C13_C12_4
802#define AMEVCNTR15_EL0 S3_3_C13_C12_5
803#define AMEVCNTR16_EL0 S3_3_C13_C12_6
804#define AMEVCNTR17_EL0 S3_3_C13_C12_7
805#define AMEVCNTR18_EL0 S3_3_C13_C13_0
806#define AMEVCNTR19_EL0 S3_3_C13_C13_1
807#define AMEVCNTR1A_EL0 S3_3_C13_C13_2
808#define AMEVCNTR1B_EL0 S3_3_C13_C13_3
809#define AMEVCNTR1C_EL0 S3_3_C13_C13_4
810#define AMEVCNTR1D_EL0 S3_3_C13_C13_5
811#define AMEVCNTR1E_EL0 S3_3_C13_C13_6
812#define AMEVCNTR1F_EL0 S3_3_C13_C13_7
813
814/* Activity Monitor Group 1 Event Type Registers */
815#define AMEVTYPER10_EL0 S3_3_C13_C14_0
816#define AMEVTYPER11_EL0 S3_3_C13_C14_1
817#define AMEVTYPER12_EL0 S3_3_C13_C14_2
818#define AMEVTYPER13_EL0 S3_3_C13_C14_3
819#define AMEVTYPER14_EL0 S3_3_C13_C14_4
820#define AMEVTYPER15_EL0 S3_3_C13_C14_5
821#define AMEVTYPER16_EL0 S3_3_C13_C14_6
822#define AMEVTYPER17_EL0 S3_3_C13_C14_7
823#define AMEVTYPER18_EL0 S3_3_C13_C15_0
824#define AMEVTYPER19_EL0 S3_3_C13_C15_1
825#define AMEVTYPER1A_EL0 S3_3_C13_C15_2
826#define AMEVTYPER1B_EL0 S3_3_C13_C15_3
827#define AMEVTYPER1C_EL0 S3_3_C13_C15_4
828#define AMEVTYPER1D_EL0 S3_3_C13_C15_5
829#define AMEVTYPER1E_EL0 S3_3_C13_C15_6
830#define AMEVTYPER1F_EL0 S3_3_C13_C15_7
831
832/* AMCGCR_EL0 definitions */
833#define AMCGCR_EL0_CG1NC_SHIFT U(8)
834#define AMCGCR_EL0_CG1NC_LENGTH U(8)
835#define AMCGCR_EL0_CG1NC_MASK U(0xff)
836
Jeenu Viswambharan5f835912018-07-31 16:13:33 +0100837/* MPAM register definitions */
838#define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63)
Louis Mayencourt537fa852019-02-11 11:25:50 +0000839#define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31)
840
841#define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49)
842#define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48)
Jeenu Viswambharan5f835912018-07-31 16:13:33 +0100843
844#define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17)
845
Jeenu Viswambharan14c60162018-04-04 16:07:11 +0100846/*******************************************************************************
847 * RAS system registers
Sathees Balya65849aa2018-12-06 13:33:24 +0000848 ******************************************************************************/
Jeenu Viswambharan14c60162018-04-04 16:07:11 +0100849#define DISR_EL1 S3_0_C12_C1_1
Antonio Nino Diaz30399882018-07-12 13:23:59 +0100850#define DISR_A_BIT U(31)
Jeenu Viswambharan14c60162018-04-04 16:07:11 +0100851
Jeenu Viswambharan30d81c32017-12-07 08:43:05 +0000852#define ERRIDR_EL1 S3_0_C5_C3_0
Antonio Nino Diaz30399882018-07-12 13:23:59 +0100853#define ERRIDR_MASK U(0xffff)
Jeenu Viswambharan30d81c32017-12-07 08:43:05 +0000854
855#define ERRSELR_EL1 S3_0_C5_C3_1
856
857/* System register access to Standard Error Record registers */
858#define ERXFR_EL1 S3_0_C5_C4_0
859#define ERXCTLR_EL1 S3_0_C5_C4_1
860#define ERXSTATUS_EL1 S3_0_C5_C4_2
861#define ERXADDR_EL1 S3_0_C5_C4_3
Antonio Nino Diaz932b3ae2018-11-22 15:53:17 +0000862#define ERXPFGF_EL1 S3_0_C5_C4_4
863#define ERXPFGCTL_EL1 S3_0_C5_C4_5
864#define ERXPFGCDN_EL1 S3_0_C5_C4_6
Jan Dabros30125ea2018-08-30 13:52:23 +0200865#define ERXMISC0_EL1 S3_0_C5_C5_0
866#define ERXMISC1_EL1 S3_0_C5_C5_1
Jeenu Viswambharan30d81c32017-12-07 08:43:05 +0000867
Antonio Nino Diaz932b3ae2018-11-22 15:53:17 +0000868#define ERXCTLR_ED_BIT (U(1) << 0)
869#define ERXCTLR_UE_BIT (U(1) << 4)
870
871#define ERXPFGCTL_UC_BIT (U(1) << 1)
872#define ERXPFGCTL_UEU_BIT (U(1) << 2)
873#define ERXPFGCTL_CDEN_BIT (U(1) << 31)
874
875/*******************************************************************************
876 * Armv8.3 Pointer Authentication Registers
Sathees Balya65849aa2018-12-06 13:33:24 +0000877 ******************************************************************************/
Antonio Nino Diaz52839622019-01-31 11:58:00 +0000878#define APIAKeyLo_EL1 S3_0_C2_C1_0
879#define APIAKeyHi_EL1 S3_0_C2_C1_1
880#define APIBKeyLo_EL1 S3_0_C2_C1_2
881#define APIBKeyHi_EL1 S3_0_C2_C1_3
882#define APDAKeyLo_EL1 S3_0_C2_C2_0
883#define APDAKeyHi_EL1 S3_0_C2_C2_1
884#define APDBKeyLo_EL1 S3_0_C2_C2_2
885#define APDBKeyHi_EL1 S3_0_C2_C2_3
Antonio Nino Diaz932b3ae2018-11-22 15:53:17 +0000886#define APGAKeyLo_EL1 S3_0_C2_C3_0
Antonio Nino Diaz52839622019-01-31 11:58:00 +0000887#define APGAKeyHi_EL1 S3_0_C2_C3_1
Antonio Nino Diaz932b3ae2018-11-22 15:53:17 +0000888
Sathees Balya65849aa2018-12-06 13:33:24 +0000889/*******************************************************************************
890 * Armv8.4 Data Independent Timing Registers
891 ******************************************************************************/
892#define DIT S3_3_C4_C2_5
893#define DIT_BIT BIT(24)
894
John Tsichritzis80744482019-03-04 16:41:26 +0000895/*******************************************************************************
896 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field
897 ******************************************************************************/
898#define SSBS S3_3_C4_C2_6
899
Antonio Nino Diaz1083b2b2018-07-20 09:17:26 +0100900#endif /* ARCH_H */